Soft Post-Package Repair for Semiconductor Memory
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Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently performing post-package repairs of defective rows, as existing permanent repair methods are time and power intensive, and lack flexibility in testing non-permanent repairs.
Innovation Solution
The implementation of a soft post-package repair (SPPR) method using volatile memory elements and a fuse logic circuit to store and alter addresses on the fuse bus, allowing for non-permanent repairs and reducing the need for permanent changes to the fuse array, thereby increasing repair flexibility and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If permanent repair methods are used to repair defective rows, then repair reliability is improved, but time consumption and power consumption increase significantly
Solution Approach 1:
The patent implements a dynamic repair approach where the memory system can switch between soft repair mode (using volatile memory elements for quick, reversible repairs) and hard repair mode (using fuse logic for permanent repairs). This dynamic capability allows the system to perform time-consuming fuse-based repairs only when necessary, while using faster volatile memory-based repairs for temporary or testable issues, thereby reducing overall time consumption while maintaining repair reliability.
Solution Approach 2:
The patent enables preliminary testing of repair operations using soft repair methods before committing to permanent fuse-based repairs. The volatile memory elements allow the system to test address redirection and repair functionality temporarily, verifying that the repair works correctly before permanently altering the fuse array. This preliminary action prevents wasted time on irreversible repairs that might not be necessary or might have issues.
2Reliability
If permanent repair methods are used to repair defective rows, then repair reliability is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements a dynamic repair approach where the memory system can switch between soft repair mode (using volatile memory elements for quick, reversible repairs) and hard repair mode (using fuse logic for permanent repairs). This dynamic capability allows the system to perform power-intensive fuse-based repairs only when necessary, while using lower-power volatile memory-based repairs for temporary or testable issues, thereby reducing overall power consumption while maintaining repair reliability.
Solution Approach 2:
The patent enables preliminary testing of repair operations using soft repair methods before committing to permanent fuse-based repairs. The volatile memory elements allow the system to test address redirection and repair functionality temporarily, verifying that the repair works correctly before permanently altering the fuse array. This preliminary action prevents wasted power on irreversible repairs that might not be necessary or might have issues.
3Adaptability or versatility
If soft post-package repair is implemented using volatile memory elements, then repair flexibility is improved, but the complexity of the fuse logic circuit increases
Solution Approach 1:
The patent segments the repair functionality into two distinct parts: soft repair logic using volatile memory elements (for flexible, testable repairs) and hard repair logic using fuse arrays (for permanent repairs). This segmentation allows each part to be optimized independently - the volatile memory portion handles flexibility and testing, while the fuse portion handles permanent commitments. The segmentation reduces overall complexity by separating concerns rather than combining all repair functionality in a single complex fuse logic circuit.
Solution Approach 2:
The patent introduces volatile memory elements as an intermediary between the address input and the fuse logic circuit. This intermediary layer allows addresses to be temporarily stored and manipulated before reaching the fuse logic, enabling soft repair operations without requiring the fuse logic itself to become more complex. The volatile memory acts as a buffer that handles the flexible addressing and redirection, keeping the fuse logic relatively simple while still providing enhanced repair flexibility.
4Adaptability or versatility
If soft post-package repair is implemented, then repair flexibility is improved, but the area occupied by fuse logic circuits increases
Solution Approach 1:
The patent segments the repair functionality into two distinct parts: soft repair logic using volatile memory elements (for flexible, testable repairs) and hard repair logic using fuse arrays (for permanent repairs). This segmentation allows each part to be optimized independently - the volatile memory portion handles flexibility and testing, while the fuse portion handles permanent commitments. The segmentation reduces overall complexity by separating concerns rather than combining all repair functionality in a single complex fuse logic circuit.
Solution Approach 2:
The patent introduces volatile memory elements as an intermediary between the address input and the fuse logic circuit. This intermediary layer allows addresses to be temporarily stored and manipulated before reaching the fuse logic, enabling soft repair operations without requiring the fuse logic itself to become more complex. The volatile memory acts as a buffer that handles the flexible addressing and redirection, keeping the fuse logic relatively simple while still providing enhanced repair flexibility.
Data Source
AI summary
Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.