Soft Processor Cores Sharing Functional Circuit
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Solution Overview
Problem
The computing industry faces challenges in integrating software-driven computing devices with hardware acceleration components, such as FPGAs, due to differences in architecture, performance, power requirements, and interface features, making it difficult to achieve efficient data processing.
Innovation Solution
A data processing system that includes a hardware acceleration plane and a software plane, where multiple soft processor cores share a functional circuit, allowing for efficient processing by leveraging both software and hardware resources through a common network infrastructure and intelligent management of acceleration components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware acceleration components (such as FPGAs) are used to supplement CPU processing, then processing performance is improved, but device complexity and integration difficulty increase due to fundamentally different architectures between software-driven devices and hardware acceleration components
Solution Approach 1:
A bridge component is introduced as an intermediary between the CPU and the hardware acceleration component. This bridge translates CPU instructions into hardware acceleration component instructions and manages data transfer between the two dissimilar devices, thereby resolving the integration difficulty caused by architectural differences while maintaining improved processing performance
Solution Approach 2:
The hardware acceleration component is designed with a unified interface and instruction set that allows it to work with multiple different CPU architectures. This multi-functionality enables the same acceleration component to be integrated across different system configurations, reducing overall integration complexity despite the fundamental architectural differences
2Use of energy by moving object
If multiple soft processor cores share a functional circuit, then power consumption is reduced and resource utilization is improved, but access coordination and resource management complexity increase
Solution Approach 1:
Multiple soft processor cores are merged to share a common functional circuit, allowing them to utilize the same hardware resources simultaneously or alternately. This sharing arrangement reduces overall power consumption by avoiding duplicate circuits while improving resource utilization efficiency
Solution Approach 2:
An arbitration mechanism with feedback control is implemented to manage access to the shared functional circuit. The system monitors the state of the functional circuit and dynamically allocates access to different processor cores based on current needs, thereby coordinating resource management without significantly increasing overall system complexity
Data Source
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AI summary
A hardware acceleration component is provided that includes a plurality of hardware clusters, each hardware cluster comprising a plurality of soft processor cores and a functional circuit. The plurality of soft processor cores share the functional circuit.