Soft Programming Semiconductor Memory Cells
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Solution Overview
Problem
The erase operation in semiconductor memory devices results in a wide distribution of threshold voltages due to varying erase speeds among memory cells, leading to differences in programming efficiency and reliability.
Innovation Solution
A soft program operation is performed after erasure, with incremental step pulse programming and verify operations using different voltage levels to gradually raise threshold voltages, setting specific voltages for bit lines based on cell states to narrow the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional erase operation is performed on all memory cells of a selected cell block, then the threshold voltages of memory cells are lowered below 0V, but the distribution width of threshold voltages becomes wide due to varying erase speeds
Solution Approach 1:
The patent segments the memory cells into multiple groups and performs separate erase operations on each group. By dividing the cell block into smaller segments and erasing them individually with controlled timing, the variation in threshold voltage distribution is reduced. Each segment can be erased more uniformly, and the overall distribution width across all cells is narrowed compared to erasing the entire block simultaneously.
Solution Approach 2:
The patent performs preliminary erase operations on specific groups of memory cells before performing a soft program operation. By pre-erasing certain groups and then applying soft programming to raise their threshold voltages to a target level, the method prepares the cells in a more uniform state before subsequent programming operations, thereby reducing the overall threshold voltage distribution width.
2Manufacturing precision
If a soft program operation is performed to raise threshold voltages of erased memory cells, then the threshold voltage distribution width is reduced, but the operation complexity increases due to multiple verify operations and voltage level management
Solution Approach 1:
The soft program operation is segmented into multiple stages with different verify voltage levels. The first verify operation uses a first voltage level to identify cells needing programming, and the second verify operation uses a second voltage level to confirm completion. This staged approach manages complexity by breaking down the soft program operation into controlled steps rather than attempting a single complex operation.
Solution Approach 2:
Different voltage levels are applied to different groups of memory cells based on their individual needs. The patent applies permission voltages to bit lines of some cell groups while applying inhibition voltages to other groups during the soft program operation. This localized voltage application reduces overall operation complexity by only actively programming cells that need it, while leaving others in a standby or inhibited state.
Data Source
AI summary
An operating method of a semiconductor memory device includes erasing all memory cells of a selected cell block, performing a soft program operation on the erased memory cells by supplying a soft program pulse to word lines of the selected cell block, performing a first verify operation using a first voltage level lower than a target voltage level of the soft program operation, performing a second verify operation using the target voltage level, setting voltages of bit lines, and repeating the soft program operation, the first verify operation, the second verify operation, and an operation of setting the voltages of bit lines while raising the soft program pulse gradually.