Soft Repair Control Circuit for DRAM Refresh
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Solution Overview
Problem
Semiconductor devices, particularly DRAM, face data loss over time due to the need for frequent refresh operations to prevent information degradation, and existing repair methods are inefficient in addressing failures during these operations.
Innovation Solution
A semiconductor device with a soft repair control circuit that generates an enable signal to repair word lines with failures by comparing internal addresses during refresh operations, using redundancy word lines to replace faulty lines within specific regions, thereby preventing repetitive repairs and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repair operations are performed during refresh operations in all regions, then data integrity is improved, but device complexity and operational overhead increase due to repetitive repairs across multiple regions
Solution Approach 1:
The patent applies local quality by enabling repair operations selectively in specific regions where failures are detected, rather than uniformly across all regions. The refresh control circuit generates enable signals that are activated only for regions containing failure addresses, allowing localized repair actions that maintain data integrity while reducing unnecessary operational overhead in healthy regions.
Solution Approach 2:
The memory device is divided into multiple regions, each with its own failure address storage and repair control. This segmentation allows independent repair operations in affected regions without impacting other regions, reducing the scope of repair operations and minimizing operational overhead while maintaining reliability in all regions.
2Reliability
If repair operations are performed frequently to address failures, then reliability is improved, but loss of time increases due to repetitive repair cycles during refresh operations
Solution Approach 1:
The patent stores failure addresses in advance during test operations before the memory device is released as a product. This preliminary identification and storage of failure addresses allows the refresh control circuit to quickly determine which regions require repair during normal operation, eliminating the need for frequent diagnostic operations and reducing time loss during repair cycles.
Solution Approach 2:
The refresh control circuit automatically generates enable signals for repair operations by comparing current refresh addresses with stored failure addresses, without requiring external control signals. This self-service mechanism reduces the time overhead associated with external control and coordination, allowing faster execution of repair operations during refresh cycles.
3Reliability
If redundancy word lines are used to replace faulty word lines, then reliability is improved, but device complexity increases due to additional circuitry and control mechanisms
Solution Approach 1:
The patent implements dynamic switching between normal word lines and redundancy word lines based on the activation of enable signals during refresh operations. The repair control circuit dynamically connects redundancy word lines to replace faulty ones only when needed, rather than maintaining a static complex routing structure. This dynamic approach provides failure tolerance while minimizing the complexity of the overall circuit architecture.
Data Source
AI summary
A semiconductor device includes a soft repair control circuit configured to generate an enable signal, in response to a soft repair control signal, wherein the enable signal is enabled when first and second internal addresses counted in a refresh operation have the same combination as first and second failure addresses, and the semiconductor device also includes a core circuit including first, second, third, and fourth regions each including a plurality of word lines which are activated based on a combination of the first, the second, third, and fourth internal addresses, wherein the core circuit is configured to repair, in response to the enable signal, a word line in which a failure has occurred and which is included in a region selected among the first, second, third, and fourth regions by the third and fourth internal addresses.