Soft Repair Data Storage in Processor Cores
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Solution Overview
Problem
Processor cores face challenges in saving and restoring soft repair data due to the erasure of soft repair information when the VDD voltage supply is disconnected, which can lead to increased latency and the need to re-create soft repair information using MBIST, disrupting power-up procedures.
Innovation Solution
Storing soft repair information in an off-chip memory element outside the processor core before disconnecting the voltage supply and restoring it upon power-up, allowing the processor core to maintain operational integrity and reduce latency during power management cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft repair information is stored in on-chip registers, then the processor core can maintain operational integrity during operation, but the data is erased when voltage is disconnected causing increased latency during power-up
Solution Approach 1:
The patent introduces an off-chip memory element as an intermediary storage medium between the processor core and the persistent power source. This external memory acts as a mediator that retains soft repair information when the processor core is powered down, allowing the data to survive voltage disconnection while still being accessible when the processor needs to resume operation.
Solution Approach 2:
The patent moves the storage location of soft repair information from the on-chip dimension (registers within the processor core) to an off-chip dimension (external memory element). This spatial relocation to another dimension allows the data to persist independently of the processor's power state, resolving the contradiction between maintaining data during operation and preserving it through power cycles.
2Reliability
If MBIST is run during every power-up to regenerate soft repair information, then the processor can recover from cache failures, but the power-up procedure latency increases
Solution Approach 1:
The patent applies preliminary action by storing the soft repair information in advance in an off-chip memory element before the processor needs to power up. This pre-stored information eliminates the need to perform the time-consuming MBIST procedure during every power-up, as the repair data is already prepared and waiting to be loaded into the processor's registers.
Solution Approach 2:
The patent creates a copy of the soft repair information and stores it in an off-chip memory element. This copying mechanism allows the original data to be preserved externally while a simplified version can be quickly loaded into the processor during power-up, avoiding the need to regenerate the entire data set through MBIST each time.
3Use of energy by moving object
If voltage supply is disconnected for power management, then power consumption is reduced, but soft repair information is erased requiring re-creation
Solution Approach 1:
The off-chip memory element serves as an intermediary that decouples the processor core from the power supply for information storage purposes. This mediator allows the processor to disconnect from the power source for energy savings while the intermediary maintains the information independently, preventing data loss during power management operations.
Solution Approach 2:
The patent segments the storage function from the processing function by placing soft repair information in a separate off-chip memory element rather than keeping it exclusively in the processor's on-chip registers. This segmentation allows the processor to enter low-power states while the segmented storage component maintains data integrity independently.
Data Source
AI summary
The present invention provides a method and apparatus for saving and restoring soft repair information. One embodiment of the method includes storing soft repair information for one or more cache arrays implemented in a processor core in a memory element outside of the processor core in response to determining that a voltage supply to the processor core is to be disconnected.


