Soft Reset Signal Synchronization Across Clock Domains
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Solution Overview
Problem
In systems-on-chip with multiple clock environments, there is no effective mechanism to allow soft reset signals to cross clock boundaries without causing metastability issues or failing to reset local logic, especially when the soft reset signal's clock environment is faster than the local logic's clock environment.
Innovation Solution
An electronic device with a soft reset hold circuit in one clock environment and a synchronizer in another clock environment, where the synchronizer generates a retimed reset signal after a predetermined period to ensure synchronous deassertion, thereby addressing metastability and synchronization issues, and allowing soft and hard reset signals to be merged through a single circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a soft reset signal is transferred directly from a faster clock environment to a slower clock environment, then the reset signal can be transmitted quickly, but metastability issues occur and the reset may not be effective
Solution Approach 1:
A synchronizer circuit is introduced as an intermediary component between the faster clock environment (CPU) and the slower clock environment (functional logic). The synchronizer captures the soft reset signal from the faster clock domain and retransmits it in the slower clock domain, ensuring proper timing alignment and eliminating metastability issues while maintaining reset effectiveness.
Solution Approach 2:
The synchronizer performs preliminary action by capturing and holding the soft reset signal before it is applied to the functional logic. This preliminary capture ensures that the reset signal is stable and properly synchronized to the slower clock domain before affecting the target logic, preventing timing-related failures.
2Reliability
If multiple separate reset synchronizers are used for different clock domains, then each clock domain receives properly synchronized reset signals, but the device complexity increases
Solution Approach 1:
Multiple reset synchronizers are merged into a single unified synchronizer circuit that handles soft reset signals for multiple clock domains. This consolidated approach maintains proper synchronization for each clock domain while reducing the overall number of separate synchronizer components, thereby lowering device complexity.
Solution Approach 2:
The synchronizer is designed with multi-functionality to serve multiple clock domains simultaneously. It can capture and retransmit reset signals to different clock environments (first and second clock domains) through a single unified structure, eliminating the need for separate dedicated synchronizers for each domain.
Data Source
AI summary
An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.