Soft-Start Circuit Using Digital-to-Analog Converter for Inrush Current Control
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Solution Overview
Problem
Conventional soft-start circuits for converters are prone to rise-time variations due to PVT variations and often require oversized RC filters to manage inrush currents, which can lead to unpredictable ramp-up phases and increased silicon area occupation.
Innovation Solution
A digital-to-analog converter is used to generate a variable-frequency output signal that controls the ramp-up phase of converters, allowing for configurable inrush current limitation and reduced silicon area occupation by decoupling the output node from the input nodes once the desired voltage is reached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If RC filters are used to limit inrush current, then inrush current is limited, but rise-time becomes dependent on PVT variations and silicon area increases
Solution Approach 1:
The patent uses a Digital-to-Analog Converter (DAC) to generate a programmable reference voltage that ramps up over a configurable number of clock cycles. By changing the digital control parameters (number of clock cycles, ramp slope), the inrush current limitation can be adjusted without changing the physical circuit structure, thus avoiding the need for oversized RC filters while maintaining precise control over the rise-time.
Solution Approach 2:
The patent replaces the passive RC filter mechanism with an active digital control system. Instead of relying on the physical properties of resistors and capacitors (which are subject to PVT variations), the system uses a digitally controlled voltage ramp generated by a DAC, providing deterministic and programmable inrush current limitation with minimal silicon area.
2Object-affected harmful factors
If RC filters are used to smooth rising edges, then inrush current is limited, but rise-time cannot be matched to converter switching frequency
Solution Approach 1:
The patent implements a dynamic and programmable rise-time control mechanism. The DAC generates a reference voltage that increases linearly over a configurable number of clock cycles, allowing the rise-time to be dynamically adjusted to match the converter's switching frequency and operating conditions. This provides adaptability that fixed RC filters cannot achieve.
Solution Approach 2:
The patent synchronizes the voltage ramp-up process with the converter's switching frequency by using a configurable number of clock cycles. The reference voltage ramps up in sync with the switching periods, ensuring that the inrush current limitation is effectively coordinated with the converter's periodic operation, something that asynchronous RC filters cannot provide.
3Object-affected harmful factors
If oversized RC filters are used to match inrush current limitation for different operating conditions, then inrush current is limited under all conditions, but silicon area and power consumption increase
Solution Approach 1:
The patent uses a programmable DAC controlled by digital parameters to adjust the inrush current limitation according to different operating conditions. By changing the digital control words, the system can optimize the ramp-up characteristics for each operating mode without requiring oversized physical components, thus minimizing both silicon area and power consumption while maintaining effective inrush current limitation across all conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides improved control over start-up time and inrush current magnitude, reducing the impact of clock mismatches and PVT variations while optimizing silicon area and power consumption.
Implementation Method 1
A digital-to-analog converter is used to generate a variable-frequency output signal that controls the ramp-up phase of converters
Data Source
AI summary
A circuit is operated by receiving an input reference signal at an input node, determining a scaling ratio based on the input reference signal, generating a digital input signal as a function of the determined scaling ratio, converting the digital input signal into an analog signal that is a scaled replica of the input reference signal, and providing the analog signal at an output node of the circuit and then, after a duration of time, coupling the input reference signal to the output node.