Analog Soft-Start Timing for LDO Undervoltage Discharge Control
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Solution Overview
Problem
In electrical systems, power management systems face challenges in detecting and reacting to undervoltage conditions in always-on voltage regulators due to the absence of digital circuits during ultra-low power modes, which are necessary to ensure reliable power management and prevent latchup conditions.
Innovation Solution
A power management system utilizing an analog soft start circuit to generate a timing signal for discharging the output capacitor after undervoltage detection, integrating a charge circuit, discharge circuit, and undervoltage detection circuit within a PMIC, and employing control logic to manage discharge time and restart the LDO regulator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If digital circuits are turned off to achieve ultra-low power modes, then quiescent currents are reduced under 10uA, but the ability to detect undervoltage conditions is lost
Solution Approach 1:
An analog comparator circuit acts as an intermediary to detect undervoltage conditions. The comparator continuously monitors the voltage at its inverting input against a reference voltage at its non-inverting input, generating an undervoltage detection signal when the monitored voltage falls below the reference threshold, thereby providing undervoltage detection capability without requiring digital circuits to remain active.
Solution Approach 2:
The patent replaces digital detection mechanisms with an analog detection mechanism. The analog comparator circuit substitutes for digital voltage monitoring, using continuous analog voltage comparison rather than digital sampling and processing to detect undervoltage conditions, thus eliminating the need for active digital circuits during ultra-low power modes.
2Use of energy by moving object
If the output capacitor is not fully discharged after undervoltage detection, then power efficiency is improved, but latchup conditions may occur compromising system reliability
Solution Approach 1:
The discharge circuit is activated in advance to fully discharge the output capacitor before allowing the LDO regulator to restart. The control logic monitors the undervoltage detection signal and maintains the discharge circuit active until the capacitor is fully discharged, preventing latchup conditions by ensuring the output voltage is below the latchup threshold before regulator reactivation.
Solution Approach 2:
The control logic uses feedback from the undervoltage detection signal to regulate the discharge process. When an undervoltage condition is detected, the control logic activates the discharge circuit and continues discharging until the condition is resolved and the capacitor is fully discharged, at which point the discharge circuit is deactivated and the regulator may restart.
3Loss of time
If an analog timer circuit is used to generate timing signals, then discharge time can be precisely controlled, but device complexity increases
Solution Approach 1:
The analog comparator circuit serves multiple functions: it detects undervoltage conditions by comparing the output voltage against a reference threshold, and it generates timing signals for the discharge process. By reusing the comparator for both detection and timing functions, the patent avoids adding separate timer circuitry, thereby maintaining precise discharge time control without significantly increasing device complexity.
Solution Approach 2:
The patent combines the undervoltage detection function and the timing signal generation function into a single analog comparator circuit. The comparator's output serves dual purposes: indicating undervoltage conditions and providing timing information for the discharge circuit control, thereby reducing overall circuit complexity while maintaining precise timing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively handles undervoltage conditions by ensuring complete discharge of the output capacitor, guaranteeing a reset condition and preventing latchup, even in the absence of digital state machines, thereby maintaining system reliability and power efficiency.
Implementation Method 1
a power management system may manage power-up and power-down of a connected system... a corresponding digital state machine and associated analog circuits such as internal bandgaps, voltage regulators, and power-on reset (POR) circuits
Implementation Method 2
the control logic includes an analog timer circuit configured to generate the timing signal, the analog timer circuit including a comparator and a reset switch
Data Source
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AI summary
Examples of an apparatus and method for power management are disclosed. In an example, a device includes a charge circuit, a discharge circuit, an undervoltage detection circuit, wherein the charge circuit and the discharge circuit are couplable to a capacitor, and wherein the charge circuit includes an analog soft start circuit, and control logic configured to determine a discharge time of the capacitor in response to a timing signal that is generated in response to a voltage from the analog soft start circuit.