Soft-Verify Write Assist Circuit for Resistive Memory
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Solution Overview
Problem
Conventional write assist circuits for resistive memory (ReRAM) face issues with over-write due to variability in bit cells, requiring long write pulses that can impact speed or damage the memory element, and involve large voltage swings and read cycles, which are inefficient and costly.
Innovation Solution
A soft-verify write assist circuit controlled by a reference voltage, word line, and switching signal, incorporating a memory cell, three-terminal switching elements, and a soft-verify controlling unit that performs verify operations without read cycles, with reduced voltage swings and no polarity changes, using a ramping and soft-verify voltage control mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long write pulse is used for set or reset process, then write effectiveness is improved, but over-write occurs which impacts speed or damages the ReRAM element
Solution Approach 1:
The patent applies periodic action by using multiple short write pulses instead of a single long pulse. The write operation is divided into discrete pulse cycles with verify operations in between, allowing the system to achieve reliable writing without the over-write problems of continuous long pulses. This is evident in the write assist circuit that applies voltage in periodic pulses with verification steps.
Solution Approach 2:
The patent implements feedback through the verify operation that checks whether the write operation has been successfully completed. The sense amplifier provides feedback about the memory cell state, and based on this feedback, the write assist circuit can determine whether additional write pulses are needed or if the write operation should be terminated, thus preventing over-write while ensuring reliable data storage.
2Measurement precision
If a read cycle is used to perform verify operation, then verification accuracy is improved, but operation time increases
Solution Approach 1:
The patent merges the verify operation with the write operation by using the same bit line and source line for both writing and verification. The write assist circuit combines the write pulse generation and verify operation into a single integrated process, eliminating the need for separate read cycles and reducing overall operation time while maintaining verification accuracy.
Solution Approach 2:
The patent applies preliminary action by performing the verify operation immediately after each write pulse during the write process itself, rather than waiting for a separate read cycle. The sense amplifier is prepared and ready to verify the write result as soon as the write pulse is applied, allowing for rapid verification without adding significant time to the overall operation.
3Productivity
If conventional write assist circuit is used, then write operation is performed, but large voltage swing occurs at bit line and source line
Solution Approach 1:
The patent applies segmentation by dividing the voltage application into controlled segments through the write assist circuit. Instead of applying full voltage directly to the bit line and source line, the circuit segments the voltage application through multiple switching elements and control logic, reducing the voltage swing stress on the memory cell while still achieving the necessary write effect.
Solution Approach 2:
The patent uses intermediary elements (the write assist circuit components including switching elements and control logic) between the voltage source and the memory cell. These intermediaries control and regulate the voltage application, reducing the direct voltage swing stress on the bit line and source line while still enabling effective write operations to the memory cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient write operations without read cycles, reduces power consumption, and minimizes voltage swings at the bit and source lines, preventing over-write and maintaining memory integrity.
Implementation Method 1
The comparator is configured to compare a voltage level of the write data line with the reference voltage to generate a write voltage controlling signal
Implementation Method 2
The write voltage is increased in a ramping cycle and decreased in a soft-verify cycle, and the soft-verify cycle is next to the ramping cycle
Implementation Method 3
The first three-terminal switching element is switched by the switching signal to enable the ground voltage to be coupled to the source line or the bit line
Implementation Method 4
The second three-terminal switching element is switched by the switching signal to enable the write data line to be coupled to the bit line or the source line
Data Source
AI summary
An operating method of the soft-verify write assist circuit of the resistive memory provides a voltage level applying step, a write operating step and a write voltage controlling step. The voltage level applying step is for applying a plurality of voltage levels to the reference voltage, the word line and the switching signal, respectively. The write operating step is for driving the memory cell to perform in a set process or a reset process via the first three-terminal switching element, the second three-terminal switching element and the soft-verify controlling unit during a write operation. The write voltage controlling step is for controlling the write voltage to be increased in the ramping cycle and decreased in the soft-verify cycle.