Softcore Processor Dynamic Instruction Generation for Accelerator Integration
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Solution Overview
Problem
Conventional methods for compiling source code for accelerators, such as FPGAs and GPGPUs, are inefficient due to long compile times and require extensive knowledge of hardware description languages, limiting the ability to optimize computationally intensive operations and extending CPU instruction sets for specific applications.
Innovation Solution
A compiler dynamically generates CPU instructions and separates source code into portions for execution by a host processor and accelerators, using annotations and simulations to identify computationally intensive operations for acceleration, and generates application-specific instructions for softcore processors to interact with logic blocks on accelerators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source code is compiled for accelerators using conventional methods, then computationally intensive operations can be accelerated, but compile times become excessively long
Solution Approach 1:
The patent segments source code into two distinct portions: computationally intensive operations that are compiled to HDL code for accelerator execution, and remaining operations that are compiled for host processor execution. This segmentation allows only the necessary portions to undergo lengthy HDL compilation, significantly reducing overall compile time while maintaining acceleration benefits for critical operations.
Solution Approach 2:
Instead of compiling entire source code to HDL, the patent applies partial action by compiling only the computationally intensive portions to HDL code for accelerator execution, while leaving other portions to be executed by the host processor. This partial compilation approach reduces compile time while providing targeted acceleration where most needed.
2Productivity
If conventional compiler methods are used for accelerators, then code can be executed on hardware, but extensive knowledge of hardware description languages is required
Solution Approach 1:
The patent introduces an intermediary compiler system that automatically identifies computationally intensive operations and translates them to HDL code without requiring the programmer to manually write or understand HDL. This intermediary layer bridges the gap between high-level source code and hardware execution, making accelerator usage accessible to programmers without extensive HDL knowledge.
Solution Approach 2:
The compiler performs self-service by automatically analyzing source code to identify computationally intensive operations and generating the appropriate HDL code portions without user intervention. The system autonomously determines which code segments require acceleration and handles the complex HDL generation process, reducing the operational burden on users.
3Adaptability or versatility
If standard CPU instruction sets are used, then code portability is maintained, but computationally intensive operations are limited in speed
Solution Approach 1:
The patent implements a dynamic code generation approach where the compiler automatically creates customized instruction sets tailored to specific computationally intensive operations. This dynamic generation allows the system to optimize for maximum execution speed in critical sections while maintaining overall code portability through the use of standard compilation workflows and host processor execution for non-critical portions.
Solution Approach 2:
The patent applies local quality by generating specialized, application-specific instructions only for the computationally intensive portions of code that are compiled to HDL, while leaving other portions to use standard instruction sets. This localized customization provides high-performance optimization where needed without sacrificing the portability and simplicity of standard compilation for the rest of the codebase.
Data Source
AI summary
In one embodiment, a method may receive, by a compiler of a host computing system, source code for a computer application. The method may also include separating a first portion of the source code and a second portion of the source code that are to be compiled for execution by an accelerator operatively coupled to the host computing system. The method may also include compiling the first portion of the source code to generate hardware description language code. A logic block is to be generated on the accelerator in view of the hardware description language code. The method also includes compiling the second portion of the source code to generate softcore processor code, and adding instructions to the softcore processor code to cause the softcore processor code to interact with the logic block during execution of the softcore processor code and the logic block.