Software ADPLL Architecture for Reconfigurable Low-Spur PLL Processing
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Solution Overview
Problem
Conventional all-digital phase locked loop (ADPLL) circuits in wireless communication systems are inflexible and difficult to reconfigure, making them unsuitable for multi-standard wireless applications, and they generate significant current transients that result in unacceptable RF spurs due to their hardwired design.
Innovation Solution
A software-based ADPLL architecture with a reconfigurable calculation unit (RCU) that can perform all atomic operations within a single reference clock cycle, using an application-specific instruction-set processor (ASIP) to enable flexible configuration and reduce current transients by operating at higher processor clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hardwired ADPLL design is used, then the circuit provides dedicated hardware for each function running at lower speed, but the design lacks reconfigurability and generates significant current transients causing RF spurs
Solution Approach 1:
The patent implements a dynamically reconfigurable ADPLL architecture where the calculation unit can be programmed to perform different atomic operations depending on the communication standard requirements. This allows the system to adapt its functionality dynamically rather than being fixed in hardware, resolving the contradiction between reliability and adaptability.
Solution Approach 2:
The patent changes the operational parameters by using a programmable calculation unit that can execute different instruction sets. The system modifies its behavior by loading different microcode or instruction sequences, enabling it to support multiple communication standards (GSM, WCDMA, LTE, etc.) while maintaining reliable RF performance through optimized parameter configurations.
2Reliability
If a hardwired ADPLL design is used, then the circuit structure is fixed, but any modification requires numerous time-consuming steps in the ASIC creation process
Solution Approach 1:
The patent employs a programmable calculation unit that can be reconfigured through software or microcode updates without requiring physical hardware changes. This dynamic approach allows modifications to be made post-manufacturing, eliminating the need for time-consuming ASIC re-spins and enabling rapid adaptation to new standards or requirements.
Solution Approach 2:
The patent uses a standardized programmable calculation unit that can be replicated across different products and standards. Instead of creating custom hardwired circuits for each application, the same hardware template is used with different programming, simplifying the manufacturing process and reducing development time.
3Speed
If a microprocessor based implementation is used, then shared hardware runs at higher speed, but the dedicated hardware implementation uses lower speed with more area
Solution Approach 1:
The patent implements a universal calculation unit that can perform multiple atomic operations required by different communication standards. This single multi-functional unit replaces what would otherwise require multiple dedicated hardware blocks, reducing silicon area while maintaining high operating speeds through a unified architecture.
Solution Approach 2:
The patent merges multiple dedicated hardware functions into a single programmable calculation unit. By combining phase detection, frequency synthesis, and control functions into one reconfigurable block, the system achieves higher speed operation with reduced area compared to distributed dedicated hardware implementations.
4Productivity
If computations are performed at the reference clock frequency, then the ADPLL operates at lower speed, but operating at higher processor clock frequencies reduces current transients
Solution Approach 1:
The patent uses a programmable calculation unit that can dynamically adjust its operating frequency and instruction execution timing. By running computations at optimized processor clock frequencies rather than being locked to the reference clock frequency, the system achieves higher productivity while the programmable nature allows optimization of current transient profiles through instruction scheduling and timing control.
Data Source
AI summary
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.