Software ADPLL Phase Calculator for Multi-Standard Low-Spur Transmission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional all-digital phase locked loop (ADPLL) circuits in wireless communication systems are inflexible and difficult to reconfigure, making them unsuitable for multi-standard wireless applications, and they generate significant current transients that result in unwanted RF spurs in the output spectrum.
Innovation Solution
A software-based ADPLL architecture with a reconfigurable calculation unit (RCU) that can perform all atomic operations within a single reference clock cycle, using an application-specific instruction-set processor (ASIP) to optimize PLL calculations and reduce silicon area and RF spurs by shifting computational tasks to higher processor clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional hardwired ADPLL circuits are used, then the circuit structure is simple and manufacturing is easier, but the adaptability to different communication standards is poor and reconfiguration is difficult
Solution Approach 1:
The patent implements a reconfigurable ADPLL architecture where the calculation unit can dynamically change its operation mode and parameters through control signals. The system transitions from fixed hardwired logic to a dynamic structure that can be programmed via instruction memory, enabling adaptation to different communication standards while maintaining a relatively simple base circuit structure.
Solution Approach 2:
The calculation unit is designed as a universal block that can perform multiple PLL-related functions by executing different instruction sequences. Through the instruction memory and control logic, the same hardware structure supports various communication standards (GSM, WCDMA, LTE, etc.), eliminating the need for separate dedicated circuits for each standard.
2Adaptability or versatility
If conventional hardwired ADPLL circuits are used, then the device complexity is low, but the ease of reconfiguration is poor
Solution Approach 1:
The patent replaces fixed mechanical/hardwired logic connections with a software-based control system. The instruction memory stores programmable instructions that control the calculation unit's behavior, allowing reconfiguration through software updates rather than physical circuit changes, thus maintaining manufacturing simplicity while enabling flexibility.
Solution Approach 2:
The system enables reconfiguration by changing operational parameters through control signals and instruction sequences rather than altering the physical circuit structure. The calculation unit's behavior is modified by changing the instructions executed and the parameters loaded into registers, allowing easy reconfiguration without remanufacturing.
3Object-affected harmful factors
If conventional ADPLL circuits operate at reference clock frequency, then the device complexity is low, but the current transients are significant causing RF spurs
Solution Approach 1:
The patent implements periodic computation cycles where the calculation unit performs PLL calculations at optimized intervals and frequencies. By structuring the computation as periodic tasks with proper timing and by utilizing higher processor clock frequencies, the system reduces current transient magnitude and shifts their frequency content away from sensitive RF bands, thereby minimizing RF spurs.
Solution Approach 2:
The system dynamically adjusts the operating frequency of the calculation unit based on the specific communication standard and operational requirements. By using a reconfigurable architecture that can operate at optimized frequencies rather than a fixed reference clock frequency, the system minimizes harmful current transients while adapting to different standards.
4Adaptability or versatility
If software-based ADPLL with reconfigurable calculation unit is used, then the adaptability to multiple standards is improved, but the device complexity increases
Solution Approach 1:
The patent segments the PLL functionality into distinct modular components: a reconfigurable calculation unit, instruction memory, and control logic. This segmentation allows each component to be optimized independently while working together to provide multi-standard operation, managing overall system complexity through modular design.
Solution Approach 2:
The instruction memory acts as an intermediary between the control logic and the calculation unit, translating high-level operational requirements into specific control signals and parameters. This intermediary layer simplifies the interface between different subsystems and enables flexible reconfiguration without increasing the fundamental hardware complexity.
Data Source
AI summary
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.