Software ADPLL Calculation Unit for Multi-Standard PLL Reconfiguration
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Solution Overview
Problem
Conventional all digital phase locked loop (ADPLL) circuits in wireless communication systems are inflexible and difficult to reconfigure, making them unsuitable for multi-standard wireless applications, and they generate significant current transients that result in unacceptable RF spurs.
Innovation Solution
A software-based ADPLL architecture with a reconfigurable calculation unit (RCU) that can perform all atomic operations within a single reference clock cycle, using an application-specific instruction-set processor (ASIP) to optimize PLL calculations and reduce silicon area and RF spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hardwired ADPLL design is used, then the circuit operates at lower speed with dedicated hardware, but it lacks reconfigurability and cannot support multi-standard wireless applications
Solution Approach 1:
The patent implements a reconfigurable calculation unit (RCU) that can dynamically change its operational characteristics through software control. The RCU includes configurable parameters such as the number of atomic computation units, pipeline depth, and operational mode, allowing the ADPLL to adapt its hardware behavior via software instructions rather than physical reconfiguration, thus achieving multi-standard support without complex hardware changes
Solution Approach 2:
The invention changes operational parameters of the calculation unit through software control. By modifying parameters such as the number of atomic computation units activated, pipeline depth, and operational modes, the system can support different wireless standards without physical reconfiguration. This is achieved through control inputs that adjust the RCU's behavior based on the required standard
2Object-affected harmful factors
If conventional ADPLL circuits are used, then the circuit structure is fixed, but it generates significant current transients that result in unacceptable RF spurs
Solution Approach 1:
The patent introduces dynamic control of the calculation unit's operation to reduce current transients. By using software-controlled timing and sequencing of atomic operations, the system can distribute current draw over time rather than having simultaneous switching activity, thereby reducing RF spur generation while maintaining the ability to support multiple standards through the same flexible architecture
Solution Approach 2:
The invention employs periodic operation of the atomic computation units within a pipelined architecture. By staggering the operation of different computation units and using controlled clocking, the system reduces peak current transients that cause RF spurs, while the periodic nature of the pipelined operation maintains processing throughput for multi-standard support
3Productivity
If a reconfigurable calculation unit with atomic computation units is used, then the system can perform all atomic operations within a single reference clock cycle, but the device complexity increases
Solution Approach 1:
The patent divides the calculation unit into multiple atomic computation units, each capable of performing specific atomic operations independently. This segmentation allows parallel processing of different operations within the same clock cycle, achieving high productivity. The modular atomic units can be selectively activated based on the required standard, managing complexity through selective instantiation
Solution Approach 2:
The atomic computation units are designed to be universal and multi-functional, capable of performing various atomic operations (addition, subtraction, multiplication, division) required by different wireless standards. This universality reduces the need for separate dedicated hardware for each operation, managing complexity while maintaining high calculation speed across multiple standards
Data Source
AI summary
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.