Software Clock Recovery for Transport Stream PCR Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock recovery methods require costly phase-locked loop circuits and external Voltage-Controlled Oscillators (VCOs, and are ineffective in IP networks with large jitter due to inaccurate arrival times of Program Clock Reference (PCR) signals.
Innovation Solution
The method employs software filtering using Exponentially Weighted Moving Average (EWMA) algorithms to track and recover the first PCR signal without a Digital Controlled Oscillator (DCO) or VCO, ensuring cyclic monitoring and adaptive clock recovery by introducing a fixed system clock source to generate a continuous local System Time Clock (STC).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase-locked loop circuit and external VCO are used for clock recovery, then clock recovery accuracy is improved, but device cost increases
Solution Approach 1:
The patent replaces the traditional hardware-based phase-locked loop circuit and Voltage-Controlled Oscillator (VCO) with a software-based clock recovery method. The software algorithm processes PCR timestamps and performs calculations to generate the local STC clock, eliminating the need for expensive external hardware components while maintaining clock recovery functionality.
Solution Approach 2:
The patent creates a virtual copy of the source end clock by using PCR timestamps as reference points. Instead of directly copying the physical clock signal through hardware, the software reconstructs the clock by calculating time differences between PCR arrivals and generating corresponding STC timestamps, achieving clock synchronization through computational replication.
2Adaptability or versatility
If traditional VCO-based clock recovery is used, then clock frequency adjustment is achieved, but performance in networks with large jitter deteriorates
Solution Approach 1:
The patent implements a dynamic clock recovery system where the software algorithm continuously adapts to network conditions. By processing each incoming PCR timestamp and calculating time differences dynamically, the system can adjust to varying network jitter and delay conditions, maintaining reliable clock recovery without the performance degradation experienced by traditional VCO-based systems.
Solution Approach 2:
The patent employs feedback mechanisms where the software continuously monitors PCR arrival times, calculates deviations from expected timing, and adjusts the generated STC clock accordingly. This closed-loop feedback approach enables the system to compensate for network jitter and maintain accurate clock synchronization, improving reliability in jittered network environments.
Data Source
AI summary
A method and device for clock recovery are disclosed. The method includes: obtaining a first Program Clock Reference (PCR) signal of a Transport Stream (TS) and comparing the first PCR with a local System Time Clock (STC) to get a first comparison signal; filtering the first comparison signal to get a second comparison signal and obtaining an updated second PCR according to the second comparison signal and a history value of the second PCR; and obtaining a recovered first PCR according to the updated second PCR, recording time of the second PCR recorded by a fixed system clock source and current time of the fixed system clock source. The technical solution of the present invention adopts software filtering and tracks the first PCR signal to realize cyclic monitoring and recover the first PCR. With the solution, clock recovery is more adaptive to network conditions.