Software-Defined LFSR for Low-Power LOC Test Compression

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Solution Overview

Problem

Current commercial EDA tools fail to effectively handle test compression for LOC delay testing, leading to excessive test power dissipation and large test data volumes, which is more challenging than single stuck-at fault testing.

Innovation Solution

A low-power test compression architecture is proposed using a deterministic built-in self-test (BIST) scheme with a software-defined linear feedback shift register (SLFSR), scan tree architecture, and gating technique, which selects a primitive polynomial and additional variables to encode deterministic test pairs and reduce test data volume.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If deterministic BIST approach is used for LOC delay testing, then test coverage is improved, but test data volume and power consumption increase significantly

Engineering Contradiction:

Improvetest coverageVSAvoidtest data volume

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines multiple test pairs into a single compressed test sequence using LFSR-based test compression. Multiple deterministic test pairs that would normally require separate application are merged into one continuous test sequence, reducing the total number of test applications and associated power consumption while maintaining complete fault coverage.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The LFSR-based test compressor serves multiple functions simultaneously: it generates pseudorandom test patterns, compresses multiple test pairs into a single sequence, and enables complete LOC delay fault coverage. This multi-functional approach eliminates the need for separate test generation and compression mechanisms.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If deterministic BIST approach is used for LOC delay testing, then test coverage is improved, but power consumption increases

Engineering Contradiction:

Improvetest coverageVSAvoidtest power dissipation

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The LFSR generates pseudorandom test patterns through periodic clock cycles, creating a continuous test sequence that systematically exercises all delay paths. This periodic operation allows complete fault coverage to be achieved through repeated cycling rather than multiple separate test applications, reducing overall power consumption.

Inventive Principle:

Principle #19Periodic action

3Quantity of substance

If LFSR with additional variables is used, then test data compression ratio is improved, but device complexity increases

Engineering Contradiction:

Improvetest data volumeVSAvoidDFT architecture complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent modifies the standard LFSR structure by injecting additional variables into the feedback polynomial, transforming it into a more powerful test generator. This parameter change allows the LFSR to encode multiple test pairs with fewer state bits, achieving higher compression ratios while the added complexity remains confined to the feedback logic.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The additional variables are nested within the LFSR feedback structure, where they modify the existing polynomial without requiring a complete redesign of the LFSR architecture. This nested approach allows the enhanced functionality to be integrated into the existing DFT framework with minimal additional complexity.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS11156662B2Software defined LFSR for LOC delay testing low-power test compression

Publication Date: 2021.10.26 TSINGHUA UNIVERSITY

AI summary

A software-defined linear feedback shift register (SLFSR) implements a low-power test compression for launch-on-capture (LOC). Each bit of an extra register controls a stage of the SLFSR. A control vector is shifted into the extra register to indicate whether a primitive polynomial contains the stage of the non-zero bit. Therefore, SLFSR can configure any primitive polynomials with different degrees by loading different control vectors without any hardware overhead. A low-power test compression method and design for testability (DFT) architecture provide LOC transition fault testing by using seed encoding scheme, low-power test application procedure and a software-defined linear-feedback shift-register (SLFSR) architecture. The seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set.