Software-Defined Packet Parser for Flexible Header Processing
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Solution Overview
Problem
Existing network switch parsers lack flexibility, which hinders efficient packet processing and header classification, as they are typically designed with fixed hardware circuits that cannot adapt to varying packet protocols and requirements.
Innovation Solution
A software-defined parser is introduced, utilizing a programmable parser state table, horizontal field selectors, comparators, and a content addressable memory (CAM) based device to selectively extract user-defined fields from packet headers and generate a parser result in a union-based structure, allowing for enhanced flexibility in packet processing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed hardware circuit parser is used, then packet processing performance is improved, but flexibility is lost
Solution Approach 1:
The patent applies dynamics by making the parser configuration changeable through a control interface. The parser state table can be dynamically reconfigured to parse different packet protocols and header formats, allowing the system to adapt its parsing behavior based on the packet type being processed while maintaining high-speed hardware-based packet processing performance.
2Speed
If a fixed hardware circuit parser is used, then processing speed is improved, but adaptability to different protocols is reduced
Solution Approach 1:
The patent implements universality by designing a parser that can handle multiple packet protocols through a reconfigurable state table. The same hardware circuit can be programmed to parse different protocols (e.g., Ethernet, IP, TCP, UDP) by loading appropriate parser definitions into the state table, making the system multi-functional while maintaining hardware-speed performance.
3Adaptability or versatility
If a reconfigurable parser is implemented, then flexibility is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the parser into distinct functional components: a parser state table for configuration, horizontal field selectors for extracting specific header fields, comparators for matching field values, and a control interface for reconfiguration. This modular segmentation manages complexity by organizing the reconfigurable elements into separate, well-defined units that can be independently controlled.
4Adaptability or versatility
If more parser components are added for flexibility, then adaptability is improved, but hardware resources are consumed
Solution Approach 1:
The patent applies merging by integrating multiple parser functions into a unified reconfigurable architecture. The horizontal field selectors, comparators, and state table work together as a coordinated system rather than separate independent components. This consolidation achieves parser flexibility while optimizing hardware resource usage by sharing common resources across different parsing functions.
Data Source
AI summary
A parser is used for parsing a header in a packet. The parser includes a plurality of horizontal field selectors, a plurality of comparators, and a content addressable memory (CAM) based device. Each of the horizontal field selectors is configured to select a first bit group. The comparators are coupled to the horizontal field selectors, respectively. Each of the comparators is configured to compare a first bit group selected by a corresponding horizontal field selector with a designated value to generate a comparison result. The CAM based device is configured to receive a plurality of comparison results generated from the comparators, and use the comparison results as a first input search data.