Software-Defined Super Cores for Energy-Efficient Single-Thread Execution
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Solution Overview
Problem
High performance cores through frequency turbo are inefficient in terms of performance per watt, and scaling core size for higher IPC (instructions per cycle) is dependent on process technology node scaling, which is costly and limits core count flexibility.
Innovation Solution
Software-defined super cores (SDC) aggregate neighboring processor cores into a virtual construct, allowing them to execute different portions of an application's instructions while maintaining the appearance of a single core, with a software framework that splits threads across these cores and hardware support for efficient memory communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequency turbo is used to achieve high performance, then performance is improved, but performance per watt efficiency deteriorates
Solution Approach 1:
The processor is segmented into multiple independent cores (e.g., first core and second core) that can execute different threads or instructions simultaneously. This segmentation allows the system to achieve high performance through parallel execution while maintaining energy efficiency by activating only the necessary number of cores based on workload demands, avoiding the need for frequency turbo boosting.
2Productivity
If core size is increased to achieve higher IPC, then instructions per cycle is improved, but dependence on process technology node scaling increases
Solution Approach 1:
Multiple processor cores are merged into a unified processor architecture that shares common resources such as instruction caches, data caches, and memory controllers. This merging approach allows the system to achieve high IPC by aggregating the capabilities of multiple cores while reducing dependence on process technology node scaling, as the cores can be designed with standardized dimensions that are less sensitive to manufacturing variations.
3Productivity
If larger cores are used to increase IPC, then single thread performance is improved, but core count flexibility deteriorates
Solution Approach 1:
The processor architecture is designed with dynamic core activation capabilities, allowing the system to activate or deactivate individual cores based on the specific workload requirements. This dynamic approach enables the system to maintain high single-thread performance when needed while providing flexibility in core count configuration, as cores can be selectively activated rather than requiring all cores to be permanently present.
Data Source
AI summary
Techniques for software defined super core usage are described. In some examples, in a super core usage each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate as a single virtual core to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently, wherein the single virtual core is to support at least one of performance throttling or power throttling.