Software-Defined Super Cores for Energy-Efficient Single-Thread Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High performance cores through frequency turbo are inefficient in terms of performance per watt, and larger cores come at the cost of core count, with existing solutions requiring extensive changes to memory execution units and caches, leading to significant instruction overheads.
Innovation Solution
Software defined super cores (SDC) aggregate neighboring cores into a 'super core' by virtually fusing them to run different portions of an application's instructions while maintaining in-order retirement, using a software and hardware solution that minimizes execution overheads and reduces dependence on process technology node scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency turbo is used to achieve high performance cores, then processing speed is improved, but performance per watt deteriorates
Solution Approach 1:
The patent segments the code execution across multiple physical cores, dividing the instruction stream into different segments that can be executed in parallel. This allows the system to achieve high performance through parallel processing rather than relying solely on frequency turbo, thereby improving performance per watt while maintaining processing speed.
Solution Approach 2:
The patent merges multiple physical cores into a logical supercore, combining their computational resources to execute a single application's instructions. This merging allows the system to achieve high performance equivalent to frequency turbo while distributing the energy consumption across multiple cores, improving overall efficiency.
2Productivity
If larger cores are built to increase IPC, then single-thread performance is improved, but core count deteriorates
Solution Approach 1:
The patent merges multiple physical cores into a logical supercore, combining their computational resources to achieve high IPC for single-thread applications. This approach maintains a high number of physical cores available for multithreaded workloads while providing supercore-level performance when needed, thus preserving both IPC and core count.
Solution Approach 2:
The patent implements dynamic core configuration where physical cores can be dynamically grouped into supercores based on workload requirements. This dynamic approach allows the system to adapt between single-thread high IPC mode and multithread high core count mode, optimizing both metrics according to actual needs.
3Adaptability or versatility
If performance and efficiency core style architectures are used, then balance between single-thread and multithread performance is improved, but design and validation complexity deteriorates
Solution Approach 1:
The patent creates a universal core design where the same physical cores can function either as individual cores or as grouped supercores. This multi-functionality eliminates the need for separate performance and efficiency core designs, reducing design and validation complexity while maintaining the ability to balance single-thread and multithread performance.
4Adaptability or versatility
If performance and efficiency core style architectures are used, then flexibility in core configuration is improved, but fixed ratio of performance and efficiency cores worsens
Solution Approach 1:
The patent implements dynamic core grouping where the ratio of supercores to individual cores can change based on workload requirements. This dynamic configuration provides flexibility without being constrained by a fixed ratio of performance and efficiency cores, allowing the system to adapt to varying computational demands.
Data Source
AI summary
Techniques for usage of software defined super cores are described. In some examples, in a super core includes a first processor core to execute a first set of instruction segments of the single threaded program, wherein the first processor core is to include a disambiguation predictor for a second processor core to predict a disambiguation of a load for the first processor core against older stores of the second processor core.