Software-Defined Super Cores for Flexible IPC and Power Efficiency
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Solution Overview
Problem
High performance cores through frequency turbo are inefficient in performance/watt, and larger cores come at the cost of core count, with existing architectures having a fixed inflexible ratio of performance and efficiency cores.
Innovation Solution
Software defined super cores (SDC) aggregate neighboring cores into a virtual construct, allowing them to run different portions of an application's instructions while maintaining in-order retirement and reducing traditional process technology node dependence on scaling core size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequency turbo is used to achieve high performance cores, then performance is improved, but performance/watt efficiency deteriorates
Solution Approach 1:
The processor is segmented into multiple independent cores that can be dynamically grouped into software-defined super-cores. Each core can be independently scheduled and executed, allowing the system to segment workloads across multiple cores rather than relying on a single large core with frequency turbo, thereby improving energy efficiency while maintaining high performance.
Solution Approach 2:
The architecture enables dynamic configuration of core groups into software-defined super-cores based on workload requirements. The system can dynamically adjust which cores are active, which are in idle states, and how they are grouped together, allowing flexible optimization of performance versus power consumption without being locked into a fixed core architecture.
2Productivity
If larger cores are built to increase IPC, then instructions per cycle is improved, but core count deteriorates
Solution Approach 1:
Instead of building a single large core with high IPC, the system segments the processing workload across multiple smaller cores. Each core executes a portion of the instruction stream independently, and the results are aggregated to achieve high overall IPC. This segmentation allows more cores to be active simultaneously, increasing total throughput without requiring any single core to be excessively large.
Solution Approach 2:
Multiple independent cores are merged into software-defined super-cores that execute instructions in parallel. The cores are virtually fused to appear as a single logical unit to the operating system, combining the IPC capabilities of individual cores to achieve high overall performance while maintaining the ability to scale core count independently of physical core size.
3Adaptability or versatility
If performance and efficiency core architectures are used, then performance requirements are balanced, but design complexity increases due to multiple core designs
Solution Approach 1:
The processor architecture is designed with universal core units that can function as either performance cores or efficiency cores depending on the software-defined super-core configuration. The same basic core design can be dynamically assigned different roles based on workload requirements, eliminating the need for separate dedicated performance and efficiency core designs and reducing overall architectural complexity.
Solution Approach 2:
The architecture uses parameter changes in the form of dynamic core grouping and scheduling to transform the functional characteristics of the processor. By changing which cores are active and how they are grouped into super-cores, the system can adjust the effective performance/efficiency ratio without changing the physical hardware design, thereby achieving adaptability without increasing design complexity.
4Device complexity
If fixed ratio of performance and efficiency cores is used, then architecture is simplified, but adaptability to different workloads deteriorates
Solution Approach 1:
The architecture transitions from a fixed core configuration to a dynamic software-defined super-core system. The operating system can dynamically configure which cores are active, how they are grouped, and which workloads are assigned to which super-cores based on real-time workload characteristics. This dynamic adaptability is achieved without complicating the underlying hardware architecture, as the flexibility is implemented through software control rather than hardware complexity.
Data Source
AI summary
Techniques for software defined super core usage are described. In some examples, a first and a second processor core are to operate as a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using a shared memory space, wherein the instruction segments are to include one or more of a store instruction to store live register data to be shared with another core and a load instruction to load live register data shared by another core.