Software-Defined Super Cores for High IPC and Power Efficiency
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Solution Overview
Problem
High performance cores through frequency turbo are inefficient in terms of performance per watt, and larger cores come at the cost of core count, with existing architectures having a fixed inflexible ratio of performance and efficiency cores.
Innovation Solution
Software defined super cores (SDC) aggregate the Instructions-per-Cycle (IPC) capabilities of neighboring cores into a 'super core' by virtually fusing them to run different portions of an application's instructions while maintaining in-order retirement, reducing process technology node dependence on scaling core size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequency turbo is used to achieve high performance cores, then performance is improved, but performance per watt efficiency deteriorates
Solution Approach 1:
The processor is segmented into different core types (performance cores and efficiency cores) with distinct architectural characteristics. Performance cores are optimized for high IPC and throughput, while efficiency cores are optimized for power consumption, allowing the system to segment workloads appropriately to achieve both high performance and energy efficiency.
Solution Approach 2:
The system dynamically schedules threads across different core types based on workload characteristics. The scheduler can dynamically migrate threads between performance and efficiency cores, adjusting the allocation in real-time to optimize the balance between performance and power consumption based on current system demands.
2Productivity
If larger (deeper/wider) high IPC cores are built, then single thread performance is improved, but core count deteriorates
Solution Approach 1:
Instead of building a single large core, the architecture segments the processing capacity into multiple smaller cores with different specializations. This allows the system to maintain high core count while achieving high single-thread performance through the coordinated operation of efficiency cores for general workloads and performance cores for demanding tasks.
Solution Approach 2:
Different cores are designed with local quality optimizations tailored to their specific functions. Efficiency cores are optimized for power efficiency and general-purpose workloads, while performance cores are optimized for high IPC and throughput. This local optimization allows each core type to excel at its intended purpose without compromising the overall system capability.
3Adaptability or versatility
If performance and efficiency core style architectures are used, then balance between single thread and multithread performance is improved, but device complexity deteriorates
Solution Approach 1:
Both performance and efficiency cores are designed to be universally schedulable and interchangeable in the context of thread placement. The scheduler treats both core types as part of a unified resource pool, assigning threads based on workload characteristics rather than core type restrictions. This universality simplifies the scheduling architecture while maintaining the ability to balance single-thread and multithread performance requirements.
Solution Approach 2:
The architecture changes key parameters such as IPC, power consumption, and core count to create distinct core types. By adjusting these parameters during the design phase, the system achieves the desired balance between performance and efficiency without requiring complex runtime configuration or migration mechanisms, thereby reducing overall device complexity.
Data Source
AI summary
Techniques for software defined super core usage are described. In some examples, in super core mode each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently.