Software-Defined Super Cores for Flexible IPC and Power Efficiency
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Solution Overview
Problem
High performance cores through frequency turbo are inefficient in terms of performance per watt, and larger cores come at the cost of core count, with existing architectures having a fixed inflexible ratio of performance and efficiency cores.
Innovation Solution
Software defined super cores (SDC) aggregate neighboring cores into a virtual construct, allowing them to run different portions of an application's instructions while maintaining in-order retirement and reducing traditional process technology node dependence on scaling core size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequency turbo is used to achieve high performance cores, then performance is improved, but performance per watt efficiency deteriorates
Solution Approach 1:
The processor is segmented into multiple independent cores that can be dynamically configured. Instead of relying on frequency turbo of a single large core, the system divides work across multiple cores, each operating at optimal frequencies, thereby improving overall performance per watt efficiency.
Solution Approach 2:
The architecture enables dynamic configuration of core combinations based on workload requirements. Cores can be dynamically activated or deactivated, and their frequencies adjusted independently, allowing the system to optimize the balance between performance and power consumption for each specific task.
2Productivity
If larger cores are built to increase IPC, then instructions per cycle is improved, but core count deteriorates
Solution Approach 1:
Instead of building a single large core with high IPC, the system uses multiple smaller cores that can be independently configured. This segmentation allows the total IPC capability to be maintained or improved while increasing the number of executable threads through parallel core activation.
Solution Approach 2:
Multiple cores are merged into a unified execution environment where their individual IPC capabilities combine to achieve high overall throughput. The system merges the execution capacity of multiple cores while maintaining their independence, effectively achieving high IPC without sacrificing core count.
3Device complexity
If performance and efficiency core architectures are designed with fixed ratio, then design simplicity is maintained, but adaptability deteriorates
Solution Approach 1:
The architecture transitions from fixed core configurations to dynamic, programmable core activation patterns. The system can adaptively configure which cores are active and their respective frequencies based on the specific workload, providing versatility while maintaining a unified core design template.
Solution Approach 2:
A single core design template serves multiple functions by being configurable in different activation patterns and frequency settings. The same physical core can function as part of a performance-optimized configuration or an efficiency-optimized configuration, making the design universally adaptable to different workloads.
Data Source
AI summary
Techniques for software defined super core usage are described. In some examples, in a super core each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by an operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently.