Software-Defined Super Cores for Higher IPC and Energy Efficiency
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Solution Overview
Problem
High performance cores through frequency turbo are inefficient in performance/watt, and larger cores come at the cost of core count, with existing solutions requiring extensive changes to memory execution units and caches, leading to significant instruction overheads.
Innovation Solution
Software-defined super cores (SDC) aggregate neighboring cores into a virtual construct, allowing them to run different portions of an application's instructions while maintaining in-order retirement and reducing traditional process technology node dependence on scaling core size, with minimal execution overheads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency turbo is used to achieve high performance cores, then processing speed is improved, but performance per watt deteriorates
Solution Approach 1:
The system segments the code execution across multiple physical cores, dividing the instruction stream into different segments that can be executed in parallel. This segmentation allows the system to achieve high performance through parallel processing rather than frequency scaling, improving performance per watt by distributing workload across multiple lower-power cores.
Solution Approach 2:
The system merges multiple physical cores into a virtual supercore, combining their computational resources to deliver high-performance capability. This merging allows the system to achieve the performance of a single high-frequency core while distributing the actual execution across multiple lower-power cores, thereby improving efficiency.
2Productivity
If larger cores are built to increase IPC, then instructions per cycle is improved, but core count deteriorates
Solution Approach 1:
The system merges multiple physical cores into a virtual supercore, combining their computational resources to achieve high IPC. Instead of relying on a single large core, the system combines the capabilities of multiple smaller cores through software coordination, maintaining high instruction throughput while preserving core count for parallel thread execution.
Solution Approach 2:
The system introduces a virtualization dimension, creating a logical supercore that spans multiple physical cores. This dimensional transformation allows the system to achieve high IPC through coordinated parallel execution across multiple cores rather than relying on single-core scaling, thus maintaining both high productivity and adequate core count.
3Adaptability or versatility
If performance and efficiency core style architectures are used, then balance between single thread and multithread performance is improved, but design and validation complexity deteriorates
Solution Approach 1:
The system implements dynamic core coordination where the virtual supercore configuration can be adjusted based on workload requirements. The software layer dynamically manages code segmentation and core assignment, allowing the system to adapt between single-thread and multi-thread performance modes without requiring multiple fixed architectural designs, thereby reducing design complexity.
4Adaptability or versatility
If performance and efficiency core style architectures are used, then flexibility in core configuration is improved, but fixed ratio of performance and efficiency cores deteriorates
Solution Approach 1:
The system implements dynamic configuration of the virtual supercore, allowing the ratio and composition of performance and efficiency cores to be adjusted based on workload requirements. The software layer can dynamically determine which physical cores to include in the virtual supercore and how to segment code among them, providing flexibility without requiring multiple fixed architectural configurations.
Data Source
AI summary
Techniques for software defined super core usage are described. In some examples, a first and a second processor core to operate as a single virtual core to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently, wherein each of the first and second processor cores is to include a shadow store buffer to track store addresses of the other core.