Software-Defined Super Cores for Flexible Performance per Watt
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Solution Overview
Problem
High performance cores through frequency turbo are inefficient in terms of performance per watt, and larger cores come at the cost of core count, with existing architectures having a fixed inflexible ratio of performance and efficiency cores.
Innovation Solution
Software defined super cores (SDC) aggregate neighboring cores into a virtual construct, allowing them to run different portions of an application's instructions while maintaining the appearance of a single core, reducing dependence on process technology node scaling and improving energy efficiency and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequency turbo is used to achieve high performance cores, then performance is improved, but energy efficiency deteriorates
Solution Approach 1:
The processor is segmented into multiple independent cores that can be dynamically configured. The patent divides the processor into first cores and second cores with different characteristics, allowing selective activation based on workload requirements. This segmentation enables the system to achieve high performance when needed while maintaining energy efficiency during lighter workloads, resolving the contradiction between performance and energy efficiency.
Solution Approach 2:
The patent implements dynamic core configuration where cores can be activated or deactivated based on real-time workload demands. The system dynamically adjusts the number of active cores and their configurations (performance vs. efficiency) to match actual performance needs, thereby optimizing the performance-per-watt ratio rather than operating at fixed high performance settings.
2Productivity
If larger cores are built to increase IPC, then instructions per cycle is improved, but core count deteriorates
Solution Approach 1:
The processor is divided into multiple smaller independent cores rather than building a single large core. Each core can be optimized for specific functions, and the collective capability of multiple cores provides the necessary IPC while maintaining higher core count. This segmentation allows the system to achieve both high instructions per cycle and high core count simultaneously.
Solution Approach 2:
The patent combines multiple cores with different characteristics (first cores and second cores) to create a hybrid architecture. By merging the strengths of different core types and allowing them to work together, the system achieves the IPC benefits of larger cores while maintaining the advantage of higher core count through the combined effort of multiple smaller cores.
3Device complexity
If performance and efficiency core architectures are designed with fixed ratio, then design complexity is reduced, but adaptability deteriorates
Solution Approach 1:
The patent implements a dynamic core configuration system where the ratio and number of performance cores versus efficiency cores can be adjusted based on workload requirements. Rather than a fixed architectural ratio, the system dynamically determines optimal core configurations, providing adaptability while maintaining manageable design complexity through standardized core modules.
Solution Approach 2:
The patent creates a universal core architecture where the same basic core design can serve multiple functions depending on configuration. The standardized core modules can be dynamically assigned different roles (performance-oriented or efficiency-oriented) based on system needs, providing versatility without requiring multiple specialized core designs, thus maintaining design simplicity.
Data Source
AI summary
Techniques for software defined super core usage are described. In some examples, a first and a second processor core are to operate as a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently, and wherein each of the first processor core and the second processor core is to record a respective list of registers modified during execution of their respective instruction segments.