Software Defined Super Cores IPC Energy Efficiency
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Solution Overview
Problem
Existing high-performance core architectures face inefficiencies in performance/watt due to dependence on process technology node scaling, leading to larger cores that compromise core count and require flexible core design ratios.
Innovation Solution
The implementation of software-defined super cores (SDC) that aggregate the Instructions-per-Cycle (IPC) capabilities of neighboring cores, allowing them to run as a virtual cluster, reducing the need for larger cores and enhancing energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger cores are built to improve IPC, then performance is improved, but core count decreases and energy efficiency deteriorates
Solution Approach 1:
The patent divides a single large core into multiple smaller cores that can operate independently. Each smaller core executes a portion of the instruction stream, allowing the system to maintain high IPC through parallel execution while using fewer transistors and consuming less power than a monolithic large core would require.
Solution Approach 2:
The patent combines multiple smaller cores into a logical unit that behaves like a single large core. By merging the execution capabilities of multiple smaller cores, the system achieves high IPC performance while maintaining the energy efficiency advantages of smaller, less power-intensive core units.
2Productivity
If process technology node scaling is increased to enable larger cores, then IPC improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the core into multiple smaller units that can be manufactured using current, less advanced process nodes. This avoids the need to manufacture larger cores requiring more aggressive scaling, thereby reducing manufacturing complexity and cost while still achieving high IPC through parallel execution of multiple smaller cores.
3Device complexity
If fixed ratio of performance and efficiency cores is used, then design is simplified, but system flexibility decreases
Solution Approach 1:
The patent implements a dynamic configuration where the number and arrangement of smaller cores within a logical unit can be adjusted based on workload requirements. This dynamic reconfigurability allows the system to adapt to different performance and power constraints without requiring a fixed design ratio, thereby increasing system flexibility while maintaining relatively simple individual core designs.
Data Source
AI summary
Techniques for software defined super cores are described. In some examples, splitting a single threaded program into a plurality of segments delineated by split points, wherein a first set of the plurality of the segments is to be executed on a first processor core and a second, different set of the plurality of the segments is to be executed on a second processor core, wherein each of the first processor core and the second processor core is to include circuitry to support the first and the second processor core to operate as a single virtual core to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using a shared memory space by inserting a split point after a defined number of instructions into the single threaded program, adjusting jump usage dependent upon a type of branches after the split point, and inserting into each segment of the plurality of segments one or more of a store instruction to store live register data to be shared with another core, a load instruction to load live register data shared by another core, and a jump instruction to jump to a starting memory address for the segment, wherein live register data is data that another core requires to execute a segment.