Software Modem Reconfiguration for Adaptive FEC and Interference Mitigation
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Solution Overview
Problem
Traditional purpose-built modems lack flexibility in configuring modem parameters, such as Forward Error Correction (FEC) iterations and Interference Mitigation, limiting their performance in high-performance computing environments.
Innovation Solution
An all software modem operating on a High-Performance Computing (HPC) platform allows for flexible configuration of demodulator parameters, including adjusting FEC parameters and increasing LDPC iterations, enabling dynamic reprocessing of data using algorithms like Recursive Least Squares or Zero Forcing, to optimize data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional purpose-built modems use fixed processing resources, then device complexity is reduced, but adaptability and performance optimization are limited
Solution Approach 1:
The patent implements dynamic configurability in the demodulator by allowing runtime adjustment of processing parameters such as FEC iteration counts, equalizer types, and interference mitigation algorithms. This enables the system to adapt to varying channel conditions and performance requirements while maintaining a unified hardware architecture that can be dynamically reconfigured through software control.
Solution Approach 2:
The system changes operational parameters of the demodulator including Forward Error Correction iterations, equalization methods, and interference mitigation settings to optimize performance for different communication scenarios. These parameter changes allow the same physical device to achieve different performance levels without hardware modification.
2Reliability
If the number of FEC iterations is increased, then data reliability is improved, but processing time and computational resources increase
Solution Approach 1:
The patent applies partial action by allowing selective increase of FEC iterations only for specific data packets or channels that require higher reliability, rather than uniformly increasing iterations for all traffic. This enables the system to achieve improved data integrity for critical communications while maintaining acceptable processing times for less time-sensitive data.
Solution Approach 2:
The system dynamically adjusts the number of FEC iterations based on real-time channel conditions, packet priority, and current processing load. When channel conditions deteriorate or packet importance increases, the system automatically increases iteration counts to improve reliability, and reduces iterations when conditions are good to maintain processing efficiency.
3Adaptability or versatility
If digital IQ data is stored and queued for reprocessing, then adaptability for optimization is improved, but memory requirements and device complexity increase
Solution Approach 1:
The patent implements preliminary action by storing digital IQ data in buffers before final processing decisions are made. This allows the system to prepare data for potential reprocessing without immediately consuming full processing resources, enabling flexible optimization decisions to be made based on initial decoding results and channel conditions.
Solution Approach 2:
The system recovers and reprocesses stored IQ data when initial decoding fails or suboptimal results are achieved. Rather than discarding failed packets, the system retrieves stored IQ data and attempts alternative processing paths such as different equalization methods or adjusted FEC parameters, thereby improving overall data recovery rates while managing memory resources efficiently.
Data Source
AI summary
A method to provide flexibility on the configuration and operation of the modulator, demodulator, and modem, where purpose-built (legacy) devices are not traditionally capable of exposing a level of control and flexibly for a user or an autonomous program for optimizing performance. Providing user or programmatic control of algorithms is traditionally not possible for purpose-built modems. Parameters such as the number of decoder iterations that are performed on Forward Error Correction (FEC), Interference Mitigation algorithm, or dynamic adjustment loop bandwidth to combat phase noise can be adjusted autonomously to optimize receiver performance. The all software modem, supported by a High-Performance Computing (HPC) architecture, removes the limitation due to the flexibility of programming resources and available performance. Unlike most purpose-built hardware, the HPC allows processing resources to dynamically be reallocated, so that as additional performance is desired, the resources may be increased and decreased as required.