Software Modem Parameter Tuning for Adaptive FEC and LDPC
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Solution Overview
Problem
Existing modems lack flexibility in configuring parameters such as the number of decoder iterations for Forward Error Correction (FEC), which limits their ability to optimize performance in high-performance computing environments.
Innovation Solution
An all software modem using flexible configuration parameters is implemented on a High-Performance Computing (HPC) platform, allowing for dynamic adjustment of demodulator parameters, FEC parameters, and increasing the number of Low-Density Parity Check (LDPC) iterations in response to decoding failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of FEC decoder iterations is fixed or limited by processing resources in purpose-built modems, then device complexity is reduced and ease of manufacture is improved, but adaptability and reliability are worsened
Solution Approach 1:
The patent implements dynamic adjustment of FEC decoder iteration parameters, allowing the all-software modem to adapt the number of iterations based on channel conditions and performance requirements. This dynamic configuration capability resolves the contradiction by enabling parameter flexibility without requiring complex hardware reconfiguration, as the adjustments are made through software control in the HPC environment.
Solution Approach 2:
The patent changes the operational parameters of the FEC decoder by allowing flexible configuration of iteration counts. This parameter change approach enables the system to optimize reliability and adaptability by adjusting the number of decoding attempts based on communication conditions, while maintaining relatively simple device architecture through software-based parameter control rather than hardware complexity.
2Reliability
If the number of LDPC iterations is increased to improve bit error rate performance, then reliability is improved, but use of energy and processing time increase
Solution Approach 1:
The patent implements dynamic control of LDPC iteration counts, allowing the system to increase iterations only when necessary to achieve target bit error rate performance. The HPC platform monitors communication conditions and adjusts iteration numbers dynamically, ensuring high reliability when needed while conserving energy during favorable channel conditions, thus resolving the contradiction between reliability and energy consumption.
Solution Approach 2:
The patent changes the iteration parameter of the LDPC decoder to optimize the trade-off between reliability and energy consumption. By allowing flexible configuration of this parameter, the system can achieve improved bit error rate performance when high reliability is required, while reducing energy consumption by lowering iteration counts when channel conditions permit, thus resolving the contradiction through parameter optimization.
3Reliability
If real-time processing and reprocessing of data is enabled to ensure error-free transmission, then reliability is improved, but productivity and processing speed are worsened
Solution Approach 1:
The patent implements dynamic reprocessing capabilities in the all-software modem, where data that fails initial decoding can be reprocessed with adjusted parameters. The HPC platform dynamically determines when reprocessing is necessary based on decoding success, enabling high reliability through selective reprocessing rather than universal reprocessing, thus maintaining productivity while improving error-free transmission rates.
Solution Approach 2:
The patent employs feedback mechanisms where decoding results are monitored and used to trigger reprocessing only when necessary. The system receives feedback on decoding success and dynamically initiates reprocessing of failed data blocks with adjusted parameters, ensuring high reliability through error correction while minimizing the impact on processing speed by avoiding unnecessary reprocessing operations.
Data Source
AI summary
A method to provide flexibility on the configuration and operation of the modulator, demodulator, and modem, where purpose-built (legacy) devices are not traditionally capable of exposing a level of control and flexibly for a user or an autonomous program for optimizing performance. Providing user or programmatic control of algorithms is traditionally not possible for purpose-built modems. Parameters such as the number of decoder iterations that are performed on Forward Error Correction (FEC), Interference Mitigation algorithm, or dynamic adjustment loop bandwidth to combat phase noise can be adjusted autonomously to optimize receiver performance. The all software modem, supported by a High-Performance Computing (HPC) architecture, removes the limitation due to the flexibility of programming resources and available performance. Unlike most purpose-built hardware, the HPC allows processing resources to dynamically be reallocated, so that as additional performance is desired, the resources may be increased and decreased as required.