Software Verification via Simulation and Model Checking
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Solution Overview
Problem
Current software system verification methods, such as closed loop simulations, have limited coverage due to the need for exhaustive testing with numerous long traces of input data, leading to significant false negatives and impractical verification times.
Innovation Solution
A data processing apparatus and method that combines closed-loop simulation and bounded-model checking techniques to verify software systems by simulating initial steps, determining a target state, and then performing verification using test vectors and control flow graphs to ensure compliance with specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If closed loop simulation is used to verify software system, then verification can be performed with limited scenarios, but verification coverage is limited leading to false negatives
Solution Approach 1:
The verification process is segmented into two distinct phases: a simulation phase that executes the software system under various scenarios to collect trace data, and a model checking phase that analyzes the collected traces to verify specifications. This segmentation allows each phase to focus on specific aspects of verification, improving overall coverage without requiring exhaustive testing of all possible scenarios.
Solution Approach 2:
The simulation phase performs preliminary execution of the software system to collect trace data before the formal model checking. By pre-executing the system under various scenarios and storing the traces, the system prepares the necessary information for subsequent verification, enabling thorough checking without re-executing all scenarios from scratch.
2Reliability
If exhaustive testing with numerous long traces of input data is performed, then verification coverage is improved, but verification time becomes impractical
Solution Approach 1:
The approach extracts only the necessary trace data from the software system execution and uses this extracted information for verification. By collecting traces during simulation and then analyzing only these relevant traces through model checking, the system avoids the need to re-execute the entire software system under all possible scenarios, significantly improving verification efficiency while maintaining comprehensive coverage.
Solution Approach 2:
The system creates a simplified model (control flow graph) that copies the essential behavior patterns from the actual software execution traces. This abstracted model can then be thoroughly analyzed using model checking techniques without requiring re-execution of the original complex software system, enabling exhaustive verification of the model while maintaining the behavior characteristics of the actual system.
3Reliability
If bounded-model checking is performed for thorough verification, then verification coverage is improved, but the complexity of the verification process increases
Solution Approach 1:
The collected execution traces serve as an intermediary between the software system and the model checking process. These traces bridge the gap by providing concrete execution examples that can be directly used in the control flow graph, simplifying the model checking process compared to requiring abstract symbolic analysis of the entire system. The traces act as a mediator that translates system behavior into verification-friendly format.
Data Source
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AI summary
A method and apparatus for verifying a software system is disclosed. In one embodiment, a data processing apparatus (100) includes a processing unit (102), and a memory unit (104) communicatively coupled to the processing unit (102). The memory unit (104) includes a simulation module (116), and a verification module (118). The simulation module (116) is configured to perform simulation of the software system for a first set of steps based on a first set of input values. The verification module (118) is configured to instantaneously determine a state of the software system is which verification of the software system is to be initiated. The verification module (118) is configured to initiate verification of the software system at the determined state, perform verification of the software system for a second set of steps based on a second set of input values, and output results of the verification of the software system on a display unit (110).