SOG Package Substrate Architecture for CTE Matching and Low Warpage
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Solution Overview
Problem
The challenge in semiconductor packaging is the warpage and thermal expansion mismatch issues caused by the use of glass cores with metal vias and organic build-up layers, leading to reliability concerns and manufacturing challenges such as delamination and warpage during thermal cycling.
Innovation Solution
The implementation of spin-on-glass (SOG) materials in both the core and build-up layers of package substrates, allowing for CTE matching and gradient formation to minimize thermal expansion mismatches, along with advanced manufacturing processes like Litho Via and dual lithography for improved scalability and adhesion, reduces warpage and enhances reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If glass cores with metal vias and organic build-up layers are used, then package stability and warpage sensitivity are improved, but thermal expansion mismatch and delamination risks increase
Solution Approach 1:
The patent modifies the chemical composition parameters of the glass material by incorporating specific metal oxides (Bi2O3, B2O3, SiO2, PbO, ZnO) in controlled proportions to adjust the coefficient of thermal expansion (CTE) of the glass core, enabling it to match with organic build-up layers and reduce thermal expansion mismatch
Solution Approach 2:
The patent creates a composite glass material system combining multiple oxide components (silica base with bismuth oxide, boron oxide, lead oxide, and zinc oxide) to achieve both mechanical stability and tailored thermal expansion properties, forming a composite structure that bridges glass core and organic layers
2Stability of the object's composition
If glass cores are used, then warpage control is improved, but CTE mismatch between glass and metal vias increases
Solution Approach 1:
The patent adjusts the CTE parameter of the glass core by varying the composition ratios of metal oxides, particularly utilizing bismuth oxide and boron oxide to tune the thermal expansion characteristics to match metal via materials while maintaining warpage control
3Productivity
If pitch scaling is increased, then bandwidth density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies localized adhesion promotion treatments and selective material properties in specific regions of the package substrate to enhance bonding strength at critical interfaces, enabling higher pitch scaling while maintaining manufacturing precision through localized quality enhancement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher pitch scaling, reduced warpage, and improved reliability by minimizing thermal expansion mismatches and delamination risks, while allowing for better device embedding and electrical performance.
Implementation Method 1
depositing a spin-on-glass (SOG) material; annealing the SOG material
Data Source
AI summary
In one embodiment, an integrated circuit package substrate includes a core layer comprising a dielectric material and a plurality of metal vias within the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus. The metal vias electrically couple a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a plurality of build-up layers on the core layer, the build-up layers comprising metal vias electrically connected to the metal vias of the core layer.