SOG Package Substrate Architecture for CTE Matching and Warpage Control
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Solution Overview
Problem
The challenge in semiconductor packaging is the warpage and thermal expansion mismatch issues caused by the use of glass cores with metal vias and organic build-up layers, leading to reliability concerns and manufacturing challenges such as delamination and warpage during thermal cycling.
Innovation Solution
The implementation of spin-on-glass (SOG) materials in both the core and build-up layers of package substrates, allowing for CTE matching and gradient control through varying dopant concentrations, along with advanced manufacturing processes like Litho Via and dual lithography, to minimize warpage and enhance scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If glass cores with metal vias and organic build-up layers are used, then package stability and warpage sensitivity are improved, but CTE mismatch and delamination issues occur during thermal cycling
Solution Approach 1:
The patent modifies the chemical composition parameters of the glass core material by adjusting the ratios of SiO2, B2O3, Al2O3, and other oxides to achieve a CTE that matches the metal vias and organic build-up layers. This parameter optimization eliminates CTE mismatch while maintaining package stability during thermal cycling.
Solution Approach 2:
The patent develops a composite glass core material system that integrates multiple oxide components (SiO2, B2O3, Al2O3, etc.) to create a material with tailored thermal and mechanical properties. This composite approach enables simultaneous achievement of CTE matching, structural stability, and thermal cycling reliability.
2Shape
If glass cores are used, then warpage control is improved, but manufacturing complexity increases due to CTE matching requirements
Solution Approach 1:
The patent simplifies manufacturing by establishing standardized glass composition formulas (e.g., SiO2: 60-80 wt%, B2O3: 10-30 wt%, Al2O3: 5-15 wt%) that inherently provide CTE matching. This parameter standardization reduces the complexity of material selection and processing while maintaining excellent warpage control.
3Productivity
If higher pitch scaling is achieved, then bandwidth density is improved, but warpage and delamination risks increase
Solution Approach 1:
The patent optimizes glass core thickness and composition parameters to maintain CTE matching and structural integrity even as pitch scales down to finer dimensions. This enables higher bandwidth density through increased I/O density while preventing warpage and delamination that typically accompany miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces CTE mismatch, improves warpage control, and enables higher pitch scaling with better reliability and electrical performance by using SOG materials to match thermal expansion coefficients and stabilize the substrate structure.
Implementation Method 1
a glass-based core layer comprising a spin-on-glass (SOG) material
Implementation Method 2
annealing the SOG material
Implementation Method 3
CTE matching and gradient control through varying dopant concentrations
Data Source
AI summary
In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.