SOI 2T2R ReRAM Cell for Leakage Path Elimination

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Solution Overview

Problem

Existing ReRAM cells face challenges with high selector size, limited endurance, and a small read window due to the need for high voltage programming, which results in impractically large array sizes and incomplete elimination of leakage paths, especially in 1T1R and 1T2R configurations.

Innovation Solution

A resistive random-access memory (ReRAM) cell using a silicon-over-insulator (SOI) substrate with two transistors and two resistors (2T2R) configuration, where MOSFETs are formed over an insulation layer, allowing for smaller transistors and reduced voltage requirements, enabling efficient programming and operation with predefined potentials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If 1T1R configuration is used to eliminate leakage paths, then reliability is improved, but area increases significantly

Engineering Contradiction:

Improveleakage path eliminationVSAvoidcell area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The memory cell is segmented into two transistors and two resistors arranged in a specific configuration where each transistor controls one resistor. This segmentation allows for better control of leakage paths while maintaining a compact area by utilizing shared bit lines and inverted bit lines across multiple cells.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent utilizes an inverted bit line configuration that operates in a complementary dimension to the standard bit line. By introducing BLB (inverted bit line) alongside BL (standard bit line), the cell achieves differential signaling that improves reliability without proportionally increasing the physical footprint, as both lines can be routed in parallel across the array.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If 2T2R configuration is used to improve read window and reliability, then reliability is improved, but area penalty increases even more than 1T2R

Engineering Contradiction:

Improveread window and reliabilityVSAvoidcell area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Adjacent memory cells share common bit lines and inverted bit lines. The BL and BLB lines are merged resources that serve multiple cells simultaneously, reducing the per-cell area overhead. The two-transistor configuration merges control functions where both transistors work together to enable differential reading, improving reliability without linearly scaling the area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The bit lines and inverted bit lines serve multiple functions: they are used for both reading and writing operations, and they serve as common pathways for multiple adjacent cells. This multi-functionality reduces the dedicated area required per cell while maintaining the 2T2R reliability benefits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If high voltage programming is used to achieve proper memory operation, then reliability is improved, but selector size increases to impractical dimensions

Engineering Contradiction:

Improvememory operation reliabilityVSAvoidselector length

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent changes the voltage parameter by introducing complementary voltage schemes on bit lines and inverted bit lines. By using differential voltage signaling and complementary programming voltages, the system achieves reliable memory operation without requiring excessively high single-ended voltages that would demand large transistor channel lengths.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The inverted bit line acts as an intermediary that enables differential operation. By introducing BLB as a complementary signal path, the system can achieve proper programming and reading through voltage differential rather than relying on single high-voltage switches, thereby reducing the required selector dimensions.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Reliability

If aggressive programming is used to overcome small read window in 1T1R, then read window is improved, but endurance decreases

Engineering Contradiction:

Improveread windowVSAvoidendurance

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

Instead of using aggressive programming that stresses the resistive element, the patent inverts the approach by using differential reading where the read operation itself provides the discrimination between states. The inverted bit line configuration allows for gentle, non-destructive reading that maintains endurance while achieving sufficient read window through differential signal detection.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS11538524B2Silicon over insulator two-transistor two-resistor in-series resistive memory cell

Publication Date: 2022.12.27 WEEBIT NANO LTD

AI summary

A resistive random-access memory (ReRAM) cell formed on a silicon over insulator substrate (SOI) is provided. The ReRAM includes a SOI substrate, a first MOSFET and a second MOSFET, each of which having a drain port, a gate port, a source port, and a bulk port. The drain port of the second MOSFET is connected to the source port of the first MOSFET; a first resistive element and a second resistive element, each having a first port and a second port, wherein the first ports of both resistive elements are connected to the drain of the first MOSFET; a first word line and a second word line connected to the gate port of the first MOSFET and the second MOSFET, respectively; and the state of the ReRAM cell is determined upon applying a predefined potential.