SOI 3D Integration via Segmented Through Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in achieving reliable and cost-effective through substrate via connections for 3D integration, particularly due to difficulties in fabricating deep silicon vias, which result in alignment issues and high topography problems during the thinning process, leading to expensive and unreliable deep Si via etch and fill processing.
Innovation Solution
The use of silicon-on-insulator (SOI) substrates to form through vias that extend from the middle of the line (MOL) interconnects to the buried oxide (BOX) layer, eliminating the need for deep Si etch and fill processes, and allowing for standard CMOS fabrication tools to perform reactive ion etch and via fill, with tungsten or sacrificial material fill, followed by bonding and thinning to achieve planarity and alignment fidelity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep silicon vias are etched and filled to enable through substrate connections, then 3D integration is achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent segments the substrate into multiple thinner layers (e.g., two 50-micron layers instead of one 100-micron layer) to reduce the depth of vias required. This segmentation allows standard etch and fill processes to be used instead of deep via processes, thereby reducing manufacturing complexity while maintaining through-substrate connectivity for 3D integration.
Solution Approach 2:
The patent introduces an additional dimensional approach by stacking multiple thinned wafers vertically. Instead of creating one deep via through a thick substrate, the solution uses multiple shallower vias across thinned layers, effectively solving the deep via problem by transitioning to a multi-layer thin-substrate architecture.
2Reliability
If deep silicon vias are formed, then through connections are enabled, but alignment precision deteriorates due to topography issues
Solution Approach 1:
By segmenting the thick substrate into multiple thinned layers, the patent eliminates the severe topography that would otherwise exist in deep via regions. Each thinned layer has minimal topography variation, enabling precise lithographic alignment and pattern formation without the distortion caused by deep via etching and filling in monolithic thick substrates.
3Ease of manufacture
If standard CMOS fabrication tools are used, then manufacturing cost is reduced, but via depth capability is limited
Solution Approach 1:
The patent resolves the via depth limitation of standard CMOS tools by segmenting the overall via depth requirement across multiple thinned wafers. Each individual via in each thinned wafer is shallow enough for standard tools, while the cumulative effect across stacked wafers achieves the equivalent of a deep through-substrate via, thereby enabling cost-effective manufacturing without specialized deep via equipment.
4Manufacturing precision
If wafer thinning is performed, then planarity is improved, but additional processing steps are required
Solution Approach 1:
The patent applies preliminary thinning action to wafers before bonding them together. By pre-thinning each wafer to the desired thickness and achieving planarity in advance, the subsequent bonding process becomes simpler and does not require complex post-bonding thinning or planarization steps, thereby reducing overall processing complexity despite adding initial thinning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of via formation, enhances alignment fidelity, and allows for efficient planarization, enabling reliable 3D semiconductor device integration with improved electrical and thermal conductivity, while avoiding the need for deep Si etch and fill processes.
Implementation Method 1
allowing for standard CMOS fabrication tools to perform reactive ion etch and via fill
Data Source
AI summary
A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.