SOI Semiconductor Device Back Bias Control
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving stable and high-speed operation for both logic circuits and SRAM memory circuits, particularly due to threshold voltage variability and dopant-induced fluctuations, which are exacerbated by the application of back bias in bulk transistors.
Innovation Solution
A semiconductor device with a thin-film BOX-SOI structure is developed, featuring a first and second field-effect transistor with different back biases applied, where the first transistor receives a forward bias and the second transistor receives a backward bias, allowing for independent control of each circuit's operation, thereby reducing threshold voltage variability and enhancing stability and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If back bias is applied to bulk transistors to control threshold voltage, then threshold voltage control is improved, but threshold voltage variability increases and operation stability deteriorates
Solution Approach 1:
The invention divides the semiconductor substrate into two distinct regions: a first region containing logic circuits and a second region containing SRAM memory circuits. Each region is independently biased through separate back bias control, allowing the logic circuits to operate at high speed while the SRAM circuits maintain stability, thus resolving the contradiction between speed and stability
Solution Approach 2:
Different back bias conditions are applied to different regions of the semiconductor substrate. The first region (logic circuits) receives a first back bias optimized for high-speed operation, while the second region (SRAM circuits) receives a second back bias optimized for stable operation. This local differentiation allows each region to have optimized characteristics without compromising the other
2Measurement precision
If back bias is applied to bulk transistors to control threshold voltage, then threshold voltage control is improved, but operation speed deteriorates
Solution Approach 1:
The semiconductor substrate is segmented into a first region for logic circuits and a second region for SRAM circuits. The first region is biased to optimize for high-speed operation while the second region is biased to optimize for stability, allowing both speed and stability to be achieved in their respective regions simultaneously
Solution Approach 2:
Different back bias conditions are applied locally to different regions: the first region receives a back bias configuration that maximizes operation speed for logic circuits, while the second region receives a back bias configuration that maximizes operation stability for SRAM circuits
3Measurement precision
If dopant concentration is increased to reduce threshold voltage variability, then threshold voltage control is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of changing the dopant concentration parameter, the invention changes the back bias parameter to control threshold voltage. By applying different back bias voltages to different regions, the threshold voltage is controlled without requiring complex dopant concentration adjustments, thereby reducing manufacturing complexity while maintaining threshold voltage control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a 16% reduction in threshold voltage variability and improves the operational stability and speed of SRAM, enabling high-speed logic circuit operation while maintaining stable memory circuit performance.
Implementation Method 1
an insulation film, a thin-film BOX layer, having a film thickness of at most 10 nm is formed on a semiconductor support substrate
Implementation Method 2
transistor characteristics can be controlled by the application of a back bias
Data Source
AI summary
To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at most 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.