SOI Integrated Circuit Back Gate Biasing for eDRAM and Logic
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Solution Overview
Problem
The use of silicon on insulator (SOI) technology in semiconductor devices, particularly in embedded dynamic random access memory (eDRAM), is limited by the grounded N+ substrate which prevents flexibility in providing back bias to extremely thin SOI (ETSOI) devices, restricting the ability to adjust threshold voltage effectively.
Innovation Solution
The fabrication of integrated circuits with field effect transistors (FETs) that include a P-type region functioning as a back gate for logic/SRAM devices, allowing for the formation of deep trench isolation structures and trench capacitors, enabling electrical connections to N+ and P-type regions for independent voltage biasing, thereby enhancing back bias flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a grounded N+ substrate is used in eDRAM fabrication, then the device structure is simplified and manufacturing is easier, but the ability to provide back bias to ETSOI devices is lost, restricting threshold voltage adjustment flexibility
Solution Approach 1:
The substrate is segmented into functionally independent regions: an N+ type substrate region for eDRAM and a P type back gate region for logic/SRAM. This segmentation allows each region to be optimized for its specific function without compromising the other, enabling both simplified eDRAM fabrication and back bias flexibility in logic devices.
Solution Approach 2:
Different electrical properties are assigned to different locations within the substrate. The N+ type substrate provides high conductivity and simple fabrication for eDRAM, while the P type region provides adjustable back bias for logic/SRAM devices. This local differentiation resolves the contradiction by allowing each area to have the quality needed for its specific purpose.
2Reliability
If deep trench isolation structures are formed to separate eDRAM and logic/SRAM regions, then device isolation and performance are improved, but manufacturing complexity increases
Solution Approach 1:
The deep trench isolation structures serve dual functions: they provide electrical isolation between eDRAM and logic/SRAM regions, and simultaneously define the boundaries of the P type back gate region. This merging of functions reduces the number of separate fabrication steps needed compared to creating isolated isolation structures and doped regions separately.
3Adaptability or versatility
If P type regions are formed in the N+ substrate to enable back bias, then threshold voltage adjustability is improved, but junction leakage may increase
Solution Approach 1:
An intrinsic or lightly-doped semiconductor layer is introduced as an intermediary between the P type back gate region and the N+ substrate. This intermediate layer acts as a buffer that reduces direct junction leakage while preserving the back bias functionality, allowing threshold voltage adjustment without the harmful effect of excessive leakage.
Data Source
AI summary
An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.