SOI Back Gate Isolation Structure for Short Channel Effect Control
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Solution Overview
Problem
The reduction of gate pitch in CMOS transistors leads to short channel effects and performance issues, and existing configurations in SOI technology struggle to effectively insulate back gates, causing potential shorts between source/drain contacts and buried semiconductor layers during the semiconductor manufacturing process.
Innovation Solution
A semiconductor structure is developed with a buried insulating layer, a buried semiconductor layer, and extended isolation structures that laterally adjoin the SOI layer and buried semiconductor layer, preventing shorts by occupying both sides of the buried semiconductor layer with a dielectric material, even if the STI structure is eroded to the buried semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate pitch is reduced to improve VLSI efficiency and reduce manufacturing cost, then productivity increases, but short channel effects worsen and device performance deteriorates
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional control by introducing a back gate structure beneath the SOI layer. This vertical dimension allows independent control of the channel from both top (front gate) and bottom (back gate), enabling effective suppression of short channel effects even at reduced gate pitches.
Solution Approach 2:
The back gate structure is nested within the substrate beneath the buried oxide layer. This nested configuration allows the back gate to be integrated into the existing device structure without increasing lateral footprint, enabling continued scaling while maintaining control over short channel effects.
2Reliability
If a buried semiconductor layer is provided under the BOX with doped back gates to control threshold voltage and suppress short channel effects, then device performance improves, but insulation between devices and back gates becomes difficult to achieve
Solution Approach 1:
The isolation structure is segmented into multiple regions with different depths: a first isolation region extending to the buried oxide layer and a second isolation region extending further to laterally adjoin the buried semiconductor layer. This segmentation allows effective electrical isolation between the back gate and source/drain contacts while maintaining the beneficial back gate control effects.
Solution Approach 2:
Different regions of the isolation structure have different properties: the first isolation region provides basic device isolation, while the second isolation region specifically provides back gate isolation. This local differentiation of isolation properties enables precise control over electrical isolation without over-complicating the overall structure.
3Reliability
If STI structures with double depths are used to control back gates effectively, then back gate control improves, but erosion of the STI structure during manufacturing may cause shorts between source/drain contacts and buried semiconductor layer
Solution Approach 1:
The patent designs the isolation structure with a second isolation region that laterally adjoins the buried semiconductor layer, creating a protective buffer zone. This beforehand cushioning ensures that even if erosion occurs during manufacturing processes, the source/drain contacts remain isolated from the buried semiconductor layer, preventing shorts while maintaining back gate control.
Solution Approach 2:
The extended second isolation region acts as a preliminary protective measure against potential erosion. By pre-positioning this isolation barrier, the structure anticipates and counteracts the harmful effect of erosion before it can cause shorts, ensuring manufacturing robustness.
Data Source
AI summary
Semiconductor structure and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device is formed on an SOI substrate comprising an SOI layer, a buried insulating layer, a buried semiconductor layer and a semiconductor substrate from top to bottom, and comprises: source/drain regions formed in the SOI layer; a gate formed on the SOI layer, wherein the source/drain regions are located at both sides of the gate; a back gate region formed by a portion of the buried semiconductor layer which is subjected to resistance reduction; and a first isolation structure and a second isolation structure which are located at both sides of the source/drain regions and extend into the SOI substrate; wherein the first isolation structure and the second isolation structure laterally adjoin the SOI layer at a first side surface and a second side surface respectively; the first isolation structure laterally adjoins the buried semiconductor layer at a third side surface; and the third side surface is located between the first side surface and the second side surface.