SOI CTAT Current Mirror Using Back-Gate Threshold Control
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Solution Overview
Problem
Existing reference circuits require precise resistors and constant reference voltages to maintain a stable reference current over temperature, which can be costly and complex to implement, and MOS-based circuits face accuracy issues due to parasitic diodes and area inefficiencies.
Innovation Solution
A circuit utilizing fully depleted SOI transistors in current mirror configurations with self-biased back gate contacts generates a CTAT current that is relatively linear over a wide temperature range, combining with a PTAT current to produce a reference current or voltage that is stable over a wide temperature range without requiring bipolar devices or additional manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precise resistors and constant reference voltages are used to maintain stable reference current over temperature, then reference current stability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The back gate of the first SOI transistor is connected to its own drain terminal, creating a self-biasing configuration. This self-service connection automatically adjusts the threshold voltage based on the transistor's operating conditions, eliminating the need for external precise resistors and reference voltage sources to stabilize the current over temperature variations.
Solution Approach 2:
The invention changes the electrical parameters of the transistor by utilizing the back gate voltage to dynamically adjust the threshold voltage. This parameter change allows the transistor to compensate for temperature effects on current stability without requiring additional precision components, thereby reducing circuit complexity while maintaining reliability.
2Ease of manufacture
If MOS-based circuits are used for reference current generation, then manufacturing simplicity is improved, but accuracy deteriorates due to parasitic diodes
Solution Approach 1:
The invention extracts and utilizes the back gate terminal of the SOI transistor, which is physically separated from the main channel due to the buried oxide layer. This extraction allows the back gate to be independently biased to compensate for parasitic diode effects, thereby improving current accuracy while maintaining the manufacturing simplicity of standard SOI CMOS processes.
Solution Approach 2:
The invention converts the harmful parasitic diode effects into a beneficial mechanism by using the back gate voltage to actively compensate for the threshold voltage shifts caused by these parasitics. The self-biasing connection transforms the parasitic effects into a feedback mechanism that stabilizes the current, turning a manufacturing advantage (simple SOI process) into an accurate reference current source.
3Temperature
If fully depleted SOI transistors with self-biased back gate are used to generate CTAT current, then temperature stability is improved, but device area increases
Solution Approach 1:
The SOI transistor in the invention serves multiple functions simultaneously: it acts as the main current-carrying device, provides temperature compensation through its self-biased back gate, and generates the CTAT current characteristic. This multi-functionality achieves temperature stability without requiring additional compensation circuits or larger device areas, as the same transistor structure performs all necessary functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable reference current or voltage over a wide temperature range using SOI transistors, reducing manufacturing complexity and cost while improving accuracy by minimizing parasitic diode effects and area inefficiencies.
Implementation Method 1
The back gate contact of the first SOI transistor is connected to a gate of the second SOI transistor and a drain of the second SOI transistor so as to bias the back gate of the first SOI transistor at a non-zero voltage
Data Source
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AI summary
A CTAT circuit that generates a CTAT current. The circuit includes two SOI transistors of a first conductivity type arranged in a current mirror configuration where the gates of the two transistors and the back gate contact of one of the transistors is connected to the drain of the other transistor. The SOI transistor of the first conductivity type whose back gate contact is connected to the drain of the other SOI transistor of the first conductivity type is located in current path that carries a CTAT current. In some embodiments, the drains of the two transistors are each coupled to a drain of a respective one of a second pair of SOI transistors of a second conductivity type, where the second pair of SOI transistors are also configured in a current mirror configuration.