Area-Efficient Body Tie for Non-Planar SOI Floating Body Effects
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Solution Overview
Problem
Non-planar silicon-on-insulator (SOI) devices face issues with floating body effects and charge accumulation, leading to unstable threshold voltage and potential on/off state misbehavior due to the lack of efficient charge dissipation mechanisms, which complicates scaling and performance in advanced transistor designs.
Innovation Solution
The introduction of an 'area-efficient' body tie that couples the non-planar channel to a voltage potential, allowing for quick dissipation of accumulated charge and preventing floating body effects, is achieved by incorporating a thin and thick silicon region body tie adjacent to the channel, which is doped to allow conduction between the channel and the body tie while forming a diode with the source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the channel is left floating in non-planar SOI devices, then the device structure is simpler and manufacturing is easier, but charge accumulates in the channel causing floating body effects that change threshold voltage and create history effects
Solution Approach 1:
The patent extracts the charge accumulation problem by introducing a body tie that selectively couples to the channel region to remove excess charge while leaving the bulk channel floating. This extraction approach resolves the floating body effect without requiring complete channel connection, maintaining manufacturing simplicity while improving reliability.
Solution Approach 2:
The body tie acts as an intermediary element between the floating channel and the substrate. It provides a controlled path for charge dissipation while maintaining the overall floating body structure, thus resolving the contradiction between simplicity and reliability by introducing a minimal intermediate component.
2Reliability
If an area-efficient body tie is introduced to couple the channel to voltage potential, then charge dissipation improves and floating body effects are prevented, but device area is reduced
Solution Approach 1:
The body tie is implemented with local quality by positioning it specifically in regions where charge accumulation is most problematic (near source/drain junctions) while leaving other channel regions floating. This localized approach provides reliable charge dissipation where needed without occupying excessive device area.
Solution Approach 2:
The body tie extends in the vertical dimension beneath the channel rather than occupying lateral space. By utilizing the depth dimension under the gate and channel structure, the patent achieves effective charge dissipation while minimizing the lateral footprint and maintaining area efficiency.
3Reliability
If multi-gate devices with non-planar channels are used, then control of the channel is improved and short-channel effects are reduced, but floating body effects and charge accumulation problems arise
Solution Approach 1:
The channel body is segmented into different electrical states: the bulk channel remains floating to maintain multi-gate control and short-channel effect suppression, while specific regions (body tie regions) are coupled to voltage potential for charge dissipation. This segmentation resolves the contradiction by allowing different parts of the channel to serve different functions.
Solution Approach 2:
Different regions of the non-planar channel have different electrical characteristics - the main channel body is floating for optimal control, while localized body tie regions are connected to dissipate charge. This local differentiation maintains the benefits of multi-gate structures while eliminating floating body effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively dissipates accumulated charge, stabilizes the threshold voltage, and reduces the likelihood of floating body effects, thereby improving the reliability and scalability of non-planar SOI devices by minimizing area occupancy and ensuring consistent device performance.
Implementation Method 1
a body tie that is adjacent to the channel, and couples the channel to a voltage potential
Implementation Method 2
forming a diode with the source and drain regions
Data Source
AI summary
Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric.