SOI Body-Tied Source Cell Layout for Floating Body Suppression
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Solution Overview
Problem
Mobile integrated circuits (ICs) using semiconductor-on-insulator (SOI) technology face challenges due to the floating body effect, which limits switching speed and cannot be fully addressed by design or software, impacting performance and area efficiency.
Innovation Solution
The implementation of a polysilicon-shadow implant body tied to source (BTS) IC device, which utilizes a second-type implant region partially overlapping the gate region to provide a body contact and couple the source region of a second transistor to the drain region of a first transistor, reducing parasitic capacitance and area consumption through unique layout and edge implantation techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional floating body transistors are used in SOI technology, then RF performance is improved, but switching speed is limited due to the kink effect
Solution Approach 1:
The invention extracts the body region from the floating state by introducing a body contact through the gate overlap implant region, removing the harmful floating body effect while preserving the RF performance benefits of SOI technology
Solution Approach 2:
The gate overlap implant region serves as an intermediary structure that provides the body contact to tie the body to the source, enabling charge removal while maintaining the transistor's RF characteristics
2Reliability
If conventional transistor layout is used, then device functionality is achieved, but area consumption is high
Solution Approach 1:
The invention merges the body contact function with the gate structure by using the gate overlap implant region, combining multiple functions into a single integrated structure that reduces overall device area
Solution Approach 2:
The gate overlap implant region performs multiple functions simultaneously: providing body contact, coupling transistors in series, and maintaining gate control, thereby reducing the need for separate structures and minimizing area consumption
3Reliability
If standard transistor design is used, then device performance is maintained, but parasitic capacitance is high
Solution Approach 1:
The invention extracts excess parasitic capacitance by removing the floating body charge accumulation through the body contact, eliminating the harmful capacitive effects while maintaining device performance
Solution Approach 2:
The gate overlap implant region creates a localized body contact precisely where needed under the gate, providing targeted charge removal without affecting other regions of the transistor, thereby minimizing parasitic capacitance
Data Source
AI summary
An integrated circuit (IC) device is described. The IC device includes a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region. The IC device also includes a first, first-type transistor on the first-type diffusion region. The IC device further includes a second, first-type transistor on the first-type diffusion region. The IC device also includes a first, second-type implant region. The first, second-type implant region includes a gate overlap region partially overlapped with a gate region of the second, first-type transistor to provide a body contact of the second, first-type transistor and to couple a source region of the second, first-type transistor to a drain region of the first, first-type transistor in series.