Semiconductor Structure with SOI and Bulk Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor-on-insulator technology faces challenges such as the 'floating body effect' and high manufacturing costs due to the need for a selective growth process to form bulk semiconductor regions, which complicates the formation of both fully depleted and bulk field effect transistors on the same substrate.
Innovation Solution
A method is developed to form a semiconductor structure with a substrate that includes both a semiconductor-on-insulator region and a bulk region, where a replacement gate process is used without the need for a selective epitaxial growth process, allowing for the formation of transistors with gate structures of varying heights to avoid the floating body effect and reduce manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a selective growth process is used to form bulk semiconductor regions, then both fully depleted and bulk field effect transistors can be formed on the same substrate, but manufacturing costs significantly increase
Solution Approach 1:
The substrate is segmented into two distinct regions: a semiconductor-on-insulator region for fully depleted FETs and a bulk region for bulk FETs. This segmentation allows each transistor type to be formed in its optimal region without requiring complex selective growth processes across the entire substrate, thereby reducing manufacturing costs while maintaining versatility.
Solution Approach 2:
Different regions of the substrate are given different local qualities - the semiconductor-on-insulator region provides the insulating properties needed for fully depleted FETs, while the bulk region provides the bulk semiconductor properties needed for bulk FETs. This local differentiation enables both transistor types to coexist on the same substrate without requiring expensive selective growth processes.
2Reliability
If semiconductor-on-insulator technology is used, then parasitic capacitances and leakage currents are reduced, but the floating body effect occurs causing threshold voltage dependence on previous states
Solution Approach 1:
The substrate is divided into semiconductor-on-insulator and bulk regions, allowing fully depleted FETs (which avoid floating body effect) to be formed in the semiconductor-on-insulator region while bulk FETs (which are immune to floating body effect) are formed in the bulk region. This segmentation enables both transistor types to benefit from reduced parasitic capacitances and leakage currents without suffering from the floating body effect.
3Object-generated harmful factors
If fully depleted field effect transistors are formed with thin semiconductor layers, then the floating body effect is avoided, but the transistors are less suitable for some applications requiring bulk FET characteristics
Solution Approach 1:
The substrate is segmented to provide both semiconductor-on-insulator regions (for fully depleted FETs that avoid floating body effect) and bulk regions (for bulk FETs suitable for applications requiring bulk characteristics). This segmentation enables the same substrate to support both transistor types, thereby achieving both floating body effect avoidance and application versatility.
Solution Approach 2:
The semiconductor layer thickness parameter is changed differently in different regions: thin in the semiconductor-on-insulator region to achieve full depletion and avoid floating body effect, and thick in the bulk region to maintain bulk FET characteristics. This parameter variation enables both transistor types to be formed on the same substrate with optimal performance for their respective applications.
Data Source
AI summary
A semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate includes a semiconductor-on-insulator region and a bulk region. The first transistor is provided at the semiconductor-on-insulator region and includes a first gate structure and a first channel region provided in a layer of semiconductor material over a layer of electrically insulating material. The second transistor is provided at the bulk region and includes a second gate structure and a second channel region provided in a bulk semiconductor material. A plane of an interface between the second channel region and the second gate structure is not above a plane of an interface between the bulk semiconductor material and the layer of electrically insulating material in the semiconductor-on-insulator region. A height of the second gate structure is greater than a height of the first gate structure.