Silicon-on-Insulator Buried Depletion Shield Layer
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Solution Overview
Problem
In silicon-on-insulator (SOI) devices, the potential difference between well regions and the underlying semiconductor substrate can cause parasitic effects, such as depletion in Nwell regions, which can lead to circuit operation issues due to the presence of an accumulation or depletion layer at the interface of the SOI layer and the buried oxide layer.
Innovation Solution
The introduction of a p-buried region with a high-energy implantation technique, which forms a p-type layer sandwiched between the oxide layer and the n-well, helps to shield the n-well from unwanted depletion effects by creating an accumulation layer of holes when a negative voltage is applied, thereby reducing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping techniques are used to form well regions in the SOI layer, then the well regions achieve sufficient doping concentration for device operation, but potential differences between the well regions and the underlying substrate cause parasitic depletion effects at the SOI-buried oxide interface
Solution Approach 1:
A buried depletion shield layer is introduced as an intermediary structure between the Nwell region and the buried oxide layer. This shield layer, positioned at the interface region, acts as a mediator to prevent the potential difference between the Nwell and substrate from causing depletion in the Nwell. The shield layer effectively blocks the harmful electric field interaction while allowing the Nwell to maintain its required doping concentration for normal device operation.
Solution Approach 2:
The buried depletion shield layer is formed in advance during the fabrication process, before the Nwell region is fully operational. By pre-establishing this protective layer at the SOI-buried oxide interface, the patent prevents the onset of parasitic depletion effects before they can occur during circuit operation, rather than attempting to correct the problem after it arises.
2Length of moving object
If the SOI layer thickness is reduced to achieve thinner device structures, then device integration density is improved, but well regions may extend to the SOI-buried oxide interface where they are subject to unwanted depletion effects
Solution Approach 1:
The buried depletion shield layer serves as a protective intermediary that allows the SOI layer to be made thinner without compromising well region stability. By placing this shield layer at the interface region, the patent enables reduced SOI thickness while preventing the well regions from experiencing depletion effects at the interface, thus maintaining reliability despite the reduced dimension.
3Reliability
If high-energy implantation is used to form the p-buried region, then the shielding effect against depletion is enhanced, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs high-energy implantation parameters to form the p-buried region, changing the energy parameter of the implantation process to achieve deeper penetration and more effective shielding. By adjusting the implantation energy parameter, the patent creates a buried depletion shield layer that effectively counteracts depletion effects, accepting the trade-off of increased process complexity for improved device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively mitigates the parasitic effects by forming an accumulation layer of holes that shields the n-well region from depletion, ensuring stable circuit operation and preventing unwanted depletion effects.
Implementation Method 1
the presence of this potential difference will cause an accumulation layer of holes to form in the Pwell at the interface of the SOI layer and buried oxide layer
Implementation Method 2
If an Nwell is in contact with the top of the buried oxide layer, then the presence of this potential difference will cause an depletion layer to form in the Nwell
Implementation Method 3
The introduction of a p-buried region with a high-energy implantation technique, which forms a p-type layer sandwiched between the oxide layer and the n-well
Data Source
AI summary
A silicon-on-insulator device with a with buried depletion shield layer.