SOI Buried Insulating Multilayer Structure for Threshold Voltage Control
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Solution Overview
Problem
The challenge in semiconductor device manufacturing at advanced technology nodes is maintaining precise control of the threshold voltage (Vt) for optimal power consumption and performance, particularly in flash memory technologies, where scaling leads to increased noise margin, leakage current, and power consumption.
Innovation Solution
A semiconductor device structure with a buried insulating multilayer stack, including a nitride layer between silicon dioxide layers, is integrated into an SOI substrate, allowing for the formation of a back bias contact that can adjust and tune the threshold voltage through a back bias flash, enabling precise control and non-volatile tuning of the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If device dimensions are scaled down to advanced technology nodes, then switching speed and current drive behavior are improved, but threshold voltage control precision deteriorates
Solution Approach 1:
The semiconductor device is divided into multiple independently back-biasable regions, each with its own threshold voltage control mechanism. This segmentation allows precise control of threshold voltage in each region despite overall device scaling, resolving the contradiction between improved switching speed and maintained threshold voltage control precision.
Solution Approach 2:
Different regions of the semiconductor device are provided with different back bias voltages to achieve locally optimized threshold voltage characteristics. This local quality approach enables each scaled-down region to maintain precise threshold voltage control while contributing to overall improved switching speed.
2Speed
If device dimensions are scaled down, then switching behavior is improved, but leakage current increases
Solution Approach 1:
Different regions are assigned different back bias voltages to locally control leakage current while maintaining improved switching behavior. This allows the device to achieve fast switching in active regions while suppressing leakage in other regions, resolving the contradiction between switching performance and leakage current.
Solution Approach 2:
The back bias voltage parameter is dynamically adjusted in different regions to control leakage current. By changing this electrical parameter locally, the device maintains improved switching behavior while reducing leakage current in scaled-down configurations.
3Speed
If device dimensions are scaled down, then switching performance is improved, but power consumption increases
Solution Approach 1:
Different regions operate with different back bias voltages to optimize the trade-off between switching performance and power consumption. This local optimization allows the device to achieve improved switching performance where needed while reducing power consumption in other regions, resolving the contradiction between speed and energy use.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables precise control and adjustment of the threshold voltage, improving the performance and power efficiency of semiconductor devices by allowing for independent back biasing of regions, thereby reducing noise margin and leakage current.
Implementation Method 1
a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two silicon dioxide layers
Implementation Method 2
a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device
Data Source
AI summary
The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.