Conductive Layer for SOI Buried Oxide Charge Dissipation
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Solution Overview
Problem
The fabrication of photonic and optoelectronic devices on semiconductor-on-insulator (SOI) substrates is hindered by undesirable charging in the buried oxide layer, leading to issues like arcing, shifts in etching rates, and compromised measurement accuracy in electron microscopy.
Innovation Solution
Incorporating an additional electrically conducting layer in electrical contact with the buried oxide layer provides an electrical path for releasing accumulated charges, thereby mitigating charging-related issues during device fabrication and measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photonic devices are fabricated using CMOS technology on SOI substrate, then device fabrication is enabled, but charging accumulates in the buried oxide layer causing arcing and measurement errors
Solution Approach 1:
An electrically conducting layer is introduced as an intermediary between the buried oxide layer and the substrate. This conducting layer acts as a mediator to provide an electrical discharge path, allowing accumulated charges in the buried oxide layer to be safely dissipated without interfering with the photonic device fabrication process or causing harmful arcing effects.
2Productivity
If etching processes are performed on SOI substrate, then device structure is formed, but etching rates shift due to charging in buried oxide layer
Solution Approach 1:
The electrically conducting layer serves as a mediator that provides a continuous electrical discharge path through the buried oxide layer. This prevents charge accumulation that would otherwise cause etching rate shifts, thereby maintaining consistent etching rates and improving manufacturing precision throughout the etching process.
3Measurement precision
If CDSEM measurement is performed on photonic device, then critical dimensions are measured, but measurement accuracy is compromised due to charging in buried oxide layer
Solution Approach 1:
The electrically conducting layer acts as a mediator that provides an electrical discharge path, preventing charge accumulation in the buried oxide layer during CDSEM measurement. This ensures that the measurement process is not affected by charging effects, thereby maintaining high measurement accuracy for critical dimensions.
4Object-affected harmful factors
If additional electrically conducting layer is added to provide charge release path, then charging problems are addressed, but device structure complexity increases
Solution Approach 1:
The electrically conducting layer is introduced as a thin intermediary layer between the buried oxide layer and the substrate. Despite adding structural complexity, this layer provides an effective electrical discharge path that addresses charging problems. The layer can be integrated into existing fabrication processes and does not require complex additional structures or steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of the electrically conducting layer effectively addresses charging problems, preventing arcing, stabilizing etching rates, and ensuring accurate measurements of photonic and optoelectronic devices.
Implementation Method 1
forming an electrically conducting layer in electrical contact with the buried oxide layer. The electrically conducting layer may provide an electrical path for releasing an electrical charge
Data Source
AI summary
A method of fabricating a photonic device includes: forming a photonic device structure that includes a SOI substrate, which includes a bulk substrate layer, a buried oxide layer on the bulk substrate layer and an active semiconductor layer on the buried oxide layer; forming an electrically conducting layer in electrical contact of the buried oxide layer, and forming a BEOL structure on a surface of the active silicon layer.


