SOI Carrier Structure Without Frontside Chucking Layer
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Solution Overview
Problem
The fabrication of semiconductor devices requiring high operating voltages above 600 volts faces challenges due to thermally-induced stresses and strains caused by coefficient of thermal expansion (CTE) mismatches, particularly with the presence of a frontside chucking layer in silicon-on-insulator fabrication processes, which reduces manufacturing yield and increases resource requirements.
Innovation Solution
A carrier structure is developed without a frontside chucking layer, featuring a core layer of high bandgap material, a backside chucking layer, and corresponding diffusion and adhesion layers, which reduces CTE mismatches and thermally-induced stresses, thereby increasing yield and reducing resource needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a frontside chucking layer is used in silicon-on-insulator fabrication, then the wafer can be held and processed during manufacturing, but thermally-induced stresses and strains occur due to CTE mismatch, reducing manufacturing yield
Solution Approach 1:
The patent removes the frontside chucking layer from the carrier structure, extracting the source of CTE mismatch and thermally-induced stresses. The carrier structure retains only the backside chucking layer, which is sufficient for wafer handling, while eliminating the frontside layer that causes reliability issues during high voltage device fabrication.
2Ease of operation
If a frontside chucking layer is present, then wafer handling is facilitated, but resource consumption increases due to reduced yield
Solution Approach 1:
The frontside chucking layer is removed from the carrier structure, eliminating the source of thermally-induced stresses that lead to device failures and reduced yield. This extraction maintains adequate wafer handling capability through the backside chucking layer while reducing waste of semiconductor materials and manufacturing resources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturing yield of semiconductor devices by minimizing thermally-induced stresses and strains, leading to reduced resource consumption and improved efficiency in semiconductor device production.
Implementation Method 1
thermally-induced stresses and strains caused by coefficient of thermal expansion (CTE) mismatches
Data Source
AI summary
Some implementations herein describe a carrier structure and techniques of forming a semiconductor device using the carrier structure. The carrier structure includes a core layer formed from a layer of a high bandgap material, a backside layer stack formed on a backside surface of the layer of the high bandgap material, and a frontside layer stack formed on a frontside surface of the layer of the high bandgap material. The backside layer stack includes a backside chucking layer (e.g., a layer of a polysilicon material) that intervenes between a backside diffusion barrier layer and a backside adhesion layer. The frontside layer stack includes a corresponding frontside diffusion barrier layer that interfaces directly with a corresponding frontside adhesion layer. A corresponding frontside chucking layer has been eliminated. By eliminating the frontside chucking layer, a likelihood of thermally-induced stresses and/or strains due to a coefficient of thermal expansion mismatch between layers of the frontside layer stack and other layers of the semiconductor device, during formation of the semiconductor device, is reduced.