SOI Cascode LNA Rectifier Compensation for IIP3 Linearity
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Solution Overview
Problem
Current high-frequency low noise amplifiers (LNAs) face challenges in achieving high IIP3 values while maintaining gain and noise figure performance, especially in wireless communication equipment that utilizes carrier aggregation across multiple bands, and existing SiGe processes are costly and inefficient for one-chip configurations.
Innovation Solution
A high-frequency amplifier circuit using a common-source and common-gate transistor configuration with non-linear compensation circuitry, including rectifier circuits and capacitors, connected between the transistors to enhance IIP3 without significantly reducing gain or noise figure, integrated on an SOI substrate for reduced power loss and compactness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe bipolar process is used for high-frequency LNA fabrication, then electrical characteristics are improved, but manufacturing cost increases and one-chip integration with antenna switches becomes difficult
Solution Approach 1:
The patent combines the high-frequency LNA and antenna switch onto a single SOI substrate, achieving one-chip integration. This merging of previously separate components (made necessary by SiGe process limitations) onto the SOI substrate resolves the contradiction by enabling both cost-effective manufacturing and integrated design while maintaining high-frequency performance through the SOI process's low parasitic capacitance characteristics.
Solution Approach 2:
The patent changes the fabrication process parameter from SiGe bipolar to SOI CMOS, and optimizes transistor parameters (W/L ratios, bias conditions) to achieve the desired electrical characteristics. By adjusting these parameters, the invention maintains high-frequency performance suitable for 5G applications while enabling cost-effective mass production and one-chip integration.
2Reliability
If non-linear compensation circuitry is added to raise IIP3, then IIP3 value is improved, but device complexity increases
Solution Approach 1:
The non-linear compensation circuitry is segmented into distinct functional blocks: rectifier circuits for detecting signal amplitude, filtering circuits for extracting envelope information, and control circuits for adjusting amplifier gain. This segmentation allows each block to perform its specific function independently, making the overall complex system more manageable and easier to design while achieving the desired IIP3 improvement.
Solution Approach 2:
The patent introduces an intermediary control circuit that mediates between the amplifier stage and the non-linear distortion sources. This control circuit receives feedback about the amplifier's output signal characteristics and adjusts operating parameters to compensate for non-linear effects, thereby improving IIP3 without requiring complete redesign of the entire amplifier architecture.
3Power
If common-source and common-gate transistor configuration is used, then gain is improved, but noise figure may deteriorate
Solution Approach 1:
The patent applies different transistor configurations to different stages of the amplifier: common-source for maximum gain in the first stage, and common-gate for impedance matching and additional gain in subsequent stages. By optimizing the local configuration of each stage according to its specific function, the invention achieves high overall gain while managing noise figure through careful design of each individual stage's noise characteristics.
Solution Approach 2:
The amplifier uses a composite transistor configuration combining common-source and common-gate stages, leveraging the strengths of each configuration. The common-source stage provides high voltage gain, while the common-gate stage provides current gain and impedance transformation. This composite approach creates an overall amplifier structure that achieves high gain while the low parasitic capacitance of SOI transistors helps maintain acceptable noise figure performance.
Data Source
AI summary
High frequency amplifier circuitry includes a common-source first transistor to amplify a high-frequency input signal, a common-gate second transistor cascade-connected to the first transistor, to amplify a signal amplified by the first transistor to generate an output signal, a first inductor connected between a source of the first transistor and a first reference potential node, a second inductor connected between a drain of the second transistor and a second reference potential node, and non-linear compensation circuitry connected to a connection node of the first transistor and the second transistor, to compensate for non-linearity of the output signal to the high-frequency input signal. The non-linear compensation circuitry has first rectifier circuitry, a first resistor, a second resistor, second rectifier circuitry, first capacitor and second capacitor.