SOI Bipolar Cascode LNA With Bulk Regions for Lower Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 5G-NR semiconductor technologies, such as group III-V semiconductors, face challenges like high power consumption, low integration level, difficulty in mass production, and high costs, which are not adequately addressed for low noise amplifiers (LNAs) in telecommunications systems.
Innovation Solution
The use of a cascode structure with bipolar transistors on a silicon on insulator (SOI) substrate, where the buried oxide layer is locally removed to form bulk regions for improved heat dissipation, combined with high resistivity SOI substrates and thick metal layers for reduced parasitic capacitance and noise, enhances the performance of LNAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If group III-V semiconductor technologies are used for 5G LNAs, then data rates and connectivity are improved, but power consumption increases and manufacturing cost increases
Solution Approach 1:
The patent changes the material parameter from group III-V semiconductors to silicon-based materials, and changes the structural parameter by introducing a suspended membrane configuration with through-silicon vias. This parameter transformation maintains high data rate capability while reducing power consumption and enabling standard CMOS manufacturing processes.
Solution Approach 2:
The patent replaces expensive group III-V semiconductor materials with cheaper silicon-based materials that can be manufactured using standard CMOS processes. The suspended membrane structure with through-silicon vias enables mass production at lower cost while maintaining the required performance for 5G applications.
2Speed
If group III-V semiconductor technologies are used for 5G LNAs, then data rates are improved, but integration level decreases
Solution Approach 1:
The patent creates a universal platform using standard CMOS-compatible silicon-based materials and suspended membrane structures that can be integrated with existing semiconductor manufacturing processes. This multi-functional approach allows the LNA to be co-integrated with other 5G circuitry on the same chip, achieving high integration levels while maintaining high data rate performance.
Solution Approach 2:
The patent merges the LNA structure with standard CMOS fabrication processes by using suspended membrane technology and through-silicon vias. This combining approach integrates the high-frequency LNA functionality with standard digital and analog CMOS circuits on a single chip, achieving high integration levels required for 5G systems.
3Ease of manufacture
If standard SOI substrate is used, then manufacturing is simplified, but parasitic capacitance increases reducing performance
Solution Approach 1:
The patent extracts the problematic BOX layer from the standard SOI substrate, creating a suspended membrane structure. This removal eliminates the parasitic capacitance between the active device region and the substrate while maintaining the ease of manufacturing benefits of SOI technology through standard CMOS-compatible processes.
Solution Approach 2:
The patent applies local quality modification by creating through-silicon vias at specific locations to connect the suspended membrane to ground planes. This localized modification reduces parasitic capacitance in critical areas while maintaining the overall simplicity of SOI manufacturing processes.
4Quantity of substance
If bipolar transistors are placed directly on SOI substrate, then device density is improved, but heat dissipation becomes problematic
Solution Approach 1:
The patent introduces an intermediary suspended membrane structure between the bipolar transistors and the SOI substrate. This membrane acts as a thermal management intermediary, allowing heat to be dissipated more effectively through the suspended structure and through-silicon vias while maintaining high device density on the membrane surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves low power consumption, high linearity, and reduced noise figures, meeting the requirements for 5G telecommunications by optimizing the gain and bandwidth of LNAs while minimizing cross-talk and power usage.
Implementation Method 1
thick metal layers for reduced parasitic capacitance and noise
Implementation Method 2
buried oxide layer is locally removed to form bulk regions for improved heat dissipation
Data Source
AI summary
A low noise amplifier, LNA, including a silicon on insulator, SOI, substrate having a buried oxide, BOX, layer, wherein the SOI substrate includes a bulk region within which the buried oxide layer is removed. The SOI substrate is a high resistance, HR, SOI substrate including a silicon handle wafer having a resistivity greater than 3 kΩ-cm. The low noise amplifier, LNA, further has a bipolar transistor located in the bulk region, and a thick metal layer for connecting to the LNA.