SOI Handle Substrate Central Defect Concentration

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Solution Overview

Problem

Semiconductor-on-insulator (SOI) substrates face issues with wafer distortion and defects due to bulk micro defects, leading to undesirable warpage and overlay errors in photolithography processes, which affect the integrity and performance of integrated circuits.

Innovation Solution

A method of forming an SOI substrate with a handle substrate having a central region of high bulk macro defect concentration surrounded by denuded regions, where the high concentration of defects within the central region increases structural integrity and stiffness, reducing warpage and minimizing defects in the device layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If bulk micro defects are present in the handle substrate, then the substrate can be formed using conventional processes, but wafer distortion and warpage occur leading to overlay errors and reduced manufacturing precision

Engineering Contradiction:

Improveoverlay precisionVSAvoidwafer distortion

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent converts harmful bulk micro defects into beneficial bulk macro defects through a two-stage thermal process. First, bulk micro defects are formed at 500-800°C, then the substrate is heated to 1050-1150°C to grow these into large macro defects (5nm-100nm) concentrated in the central region. These macro defects increase structural integrity and stiffness, reducing wafer distortion and improving overlay precision during photolithography processes.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent creates a non-uniform distribution of defects by concentrating bulk macro defects in the central region of the handle substrate while maintaining defect-free edge regions. This local concentration strategy optimizes the balance between structural stability (provided by central defects) and device quality (preserved in edge regions), resolving the contradiction between reducing warpage and preventing defect propagation to devices.

Inventive Principle:

Principle #3Local quality

2Stability of the object's composition

If the handle substrate has high structural integrity, then wafer warpage is reduced, but this requires introducing bulk macro defects which may compromise substrate quality

Engineering Contradiction:

Improvestructural integrityVSAvoidsubstrate quality

Core Design Contradiction:

Stability of the object's compositionVSReliability

Solution Approach 1:

The patent introduces bulk macro defects selectively in the central region of the handle substrate while preserving the edge regions. This localized defect concentration provides the necessary structural integrity and stiffness to reduce wafer warpage during processing, while the defect-free edge regions maintain high substrate quality for device fabrication, thus resolving the contradiction between stability and reliability.

Inventive Principle:

Principle #3Local quality

3Strength

If conventional thermal processes are used, then processing is simple, but bulk micro defects remain small and do not provide sufficient structural support, causing warpage

Engineering Contradiction:

Improvestructural stiffnessVSAvoidthermal process complexity

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The patent performs preliminary defect formation at a lower temperature (500-800°C) to create bulk micro defects, which then serve as nuclei for subsequent growth into macro defects during a second high-temperature stage (1050-1150°C). This preliminary action simplifies the overall process by preparing the substrate in advance, enabling the defects to grow larger and provide sufficient structural stiffness without requiring overly complex processing.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces wafer distortion and overlay errors, enhancing the structural integrity of the handle substrate and improving the performance and reliability of integrated circuits by maintaining low warpage and minimizing defects in the device layer.

Implementation Method 1

the high concentration of defects within the central region increases structural integrity and stiffness, reducing warpage

Methodology Applied

Scientific EffectStructural integrity enhancement through defect concentration:

Data Source

PatentUS20220336265A1Method of forming semiconductor-on-insulator (SOI) substrate

Publication Date: 2022.10.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a handle substrate having a plurality of bulk macro defects (BMDs). An insulating layer is disposed onto a top surface of the handle substrate. A device layer, including a semiconductor material, is disposed onto the insulating layer. The handle substrate has a first denuded region and a second denuded region that vertically surround a central region of the handle substrate. The central region has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.