SOI Charge Trapping Layer Deposition With Intermittent Annealing
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Solution Overview
Problem
The existing methods for producing semiconductor-on-insulator wafers face challenges in controlling stress in the polycrystalline semiconductor layer, which can lead to crystallographic slip defects in the handle wafer, affecting the quality and suitability of the substrate for subsequent device fabrication, especially in high resistivity substrates used for RF devices.
Innovation Solution
A method involving intermittent annealing during the deposition of the semiconductor charge trapping layer, where each portion of the layer is deposited and then annealed at or near the deposition temperature, transitioning compressive stress to tensile stress, thereby reducing bow and warp and minimizing crystallographic slip defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the polycrystalline semiconductor layer is deposited continuously without interruption, then the deposition process is simple and fast, but compressive stress accumulates causing crystallographic slip defects in the handle wafer
Solution Approach 1:
The continuous deposition process is segmented into multiple interrupted cycles. The deposition is paused at intervals to allow annealing of previously deposited portions before continuing. This segmentation prevents stress accumulation that would cause crystallographic slip defects while maintaining overall process efficiency.
Solution Approach 2:
The deposition process employs periodic interruption and annealing cycles. Instead of continuous deposition, the process alternates between depositing semiconductor material and annealing the deposited layer at controlled temperatures. This periodic action transforms compressive stress to tensile stress, preventing handle wafer defects.
2Stress or pressure
If high temperature annealing is used to control stress, then stress control is effective, but crystallographic slip defects are created in the handle wafer
Solution Approach 1:
The annealing temperature parameter is precisely controlled and optimized. Instead of using high temperature annealing that causes handle wafer defects, the process uses controlled temperature annealing at or near the deposition temperature. This parameter change achieves stress control while preventing crystallographic slip defects in the handle wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively controls stress in the semiconductor-on-insulator structure, reducing bow and warp, and eliminating crystallographic slip defects, enhancing the substrate's quality and suitability for device fabrication while maintaining high resistivity.
Implementation Method 1
depositing a semiconductor charge trapping layer on a single crystal semiconductor handle substrate
Implementation Method 2
annealing the semiconductor charge trapping layer at an anneal temperature that is near or substantially equal to a deposition temperature
Data Source
AI summary
A method of preparing a multilayer structure includes providing a single crystal semiconductor handle substrate that includes a front surface, a back surface, a circumferential edge joining the front and back surfaces, and a central plane between the front and back surfaces. The single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 Ohm-cm. The method also includes depositing a semiconductor layer on the front surface of the single crystal semiconductor handle substrate. Depositing the semiconductor layer is performed by two or more cycles of depositing a portion of the semiconductor layer and interrupting the deposition after the portion of the semiconductor layer has been deposited to anneal the portion of the semiconductor layer.