SOI Semiconductor Structure With Charge Trapping for 3D Wafer Bonding
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Solution Overview
Problem
In three-dimensional integrated circuit chips, the breakdown voltage of the top wafer with input-output NMOS circuitry shifts approximately 0.8V after wafer bonding, which is a significant issue in semiconductor technology.
Innovation Solution
A semiconductor structure is developed with a silicon-on-insulator (SOI) substrate, including a device layer, a buried oxide layer, and a charge trapping layer to prevent voltage shifts. The structure features a conductive via penetrating through multiple layers and is electrically connected to the interconnect structure and the transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wafer bonding is performed to create three-dimensional integrated circuit chips, then integration density and functionality are improved, but breakdown voltage shifts occur in the top wafer
Solution Approach 1:
An intermediate layer structure is introduced between the top and bottom wafers, consisting of a charge trapping layer (containing phosphorus or boron), a capping layer, and a conductive via. This intermediary structure absorbs and traps charges that would otherwise cause breakdown voltage shifts, thereby maintaining electrical stability while enabling wafer bonding integration.
Solution Approach 2:
The charge trapping layer is formed in advance before wafer bonding, with predetermined charge trapping capabilities through doping with phosphorus or boron. This preliminary preparation ensures that when bonding occurs, the charge accumulation problem is already mitigated, preventing breakdown voltage shifts before they can occur.
2Ease of manufacture
If standard wafer bonding process is used, then manufacturing simplicity is maintained, but electrical performance degradation occurs due to breakdown voltage shift
Solution Approach 1:
The physical and chemical parameters of the intermediate layer are modified to achieve charge trapping functionality. Specifically, the charge trapping layer is doped with phosphorus or boron at controlled concentrations, and the layer thickness is optimized (capping layer: 50-150nm, charge trapping layer: 10-200nm). These parameter changes enable electrical performance control without fundamentally altering the wafer bonding process.
3Device complexity
If no charge trapping layer is present, then device complexity is reduced, but breakdown voltage instability occurs after bonding
Solution Approach 1:
A charge trapping layer serves as an intermediary component between the buried oxide layer and the active device layer. This layer, though adding structural complexity, mediates the electrical interaction by trapping charges that would otherwise cause breakdown voltage shifts, thereby significantly improving reliability.
Solution Approach 2:
The intermediate layer structure combines multiple materials with different functionalities: silicon dioxide (buried oxide layer), doped glass or silicon nitride (charge trapping layer), and metal (conductive via). This composite structure achieves both charge trapping capability and electrical conductivity, resolving the reliability issue while maintaining reasonable device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor structure effectively prevents the breakdown voltage shifting problem of the top wafer after wafer bonding, ensuring stable electrical performance in three-dimensional integrated circuit chips.
Implementation Method 1
a charge trapping layer being contiguous with the buried oxide layer
Data Source
AI summary
A semiconductor structure includes a SOI substrate having a device layer and a buried oxide layer contiguous with the device layer; a transistor disposed on the device layer; a dielectric layer surrounding the transistor; an interconnect structure disposed on the dielectric layer and electrically connected to a gate of the transistor; a charge trapping layer contiguous with the buried oxide layer; a capping layer contiguous with the charge trapping layer; and a conductive via penetrating through the capping layer, the charge trapping layer, the buried oxide layer, the device layer, and the dielectric layer. The conductive via is electrically connected to the interconnect structure.