High-Resistivity SOI Structure With Charge Trapping Layer for RF Losses
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Solution Overview
Problem
Existing methods for producing semiconductor-on-insulator (SOI) wafers are time-consuming, costly, and lack suitable thickness uniformity, especially for layers thinner than a few microns. Additionally, high resistivity SOI wafers used in RF devices suffer from parasitic power losses due to charge inversion or accumulation layers at the buried oxide/handle interface.
Innovation Solution
A method is developed to engineer the single crystal semiconductor handle substrate by depositing a polycrystalline silicon charge trapping layer (CTL) between the high resistivity handle substrate and the buried oxide. This CTL is designed to trap charges and improve the electrical performance of RF devices by maintaining high resistivity even in the near-surface region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If wafer bonding and thermal annealing are used to produce SOI structures, then the bond strength is improved, but the processing time and cost increase significantly
Solution Approach 1:
The patent applies preliminary action by performing ion implantation to create a damage layer in the donor wafer before bonding. This pre-prepared damage layer serves as a predetermined cleavage plane that enables subsequent easy separation, eliminating the need for time-consuming thermal annealing processes while ensuring strong initial bonding through van der Waals forces.
Solution Approach 2:
The patent replaces the thermal field (thermal annealing) with a mechanical field approach. Instead of using heat to strengthen bonds and create cleavage planes, the invention uses mechanical ion implantation to create a damage layer that serves as a pre-defined cleavage plane, enabling separation through mechanical stress rather than thermal processing.
2Reliability
If high resistivity handle substrates are used for RF devices, then device isolation is improved, but parasitic power losses increase due to charge inversion layers at the oxide/handle interface
Solution Approach 1:
The patent extracts the problematic charge inversion layer by introducing a charge trapping layer between the handle substrate and buried oxide. This charge trapping layer captures and neutralizes the inversion charges that would otherwise form at the oxide/handle interface, eliminating the source of parasitic power losses while preserving the high resistivity and isolation properties of the handle substrate.
Solution Approach 2:
The charge trapping layer serves as an intermediary between the handle substrate and buried oxide, mediating the electrical interaction at the interface. It traps charges that would otherwise create inversion layers, thereby preventing parasitic power losses while allowing the high resistivity handle substrate to maintain its device isolation function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a thermally stable charge trapping layer in the SOI structure significantly enhances the performance of RF devices by reducing parasitic power losses and improving device isolation, while also maintaining the high resistivity of the substrate.
Implementation Method 1
depositing a polycrystalline silicon charge trapping layer (CTL) between the high resistivity handle substrate and the buried oxide. This CTL is designed to trap charges
Implementation Method 2
bonded by van der Waal's forces
Implementation Method 3
followed by a thermal treatment to strengthen the bond. The anneal may convert the terminal silanol groups to siloxane bonds between the two interfaces
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~3D
AI summary
A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.