SOI Substrate Charge Trapping for High RF Resistivity
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Solution Overview
Problem
High resistivity silicon-on-insulator wafers used in RF devices suffer from charge inversion or accumulation layers at the buried oxide interface, leading to parasitic power losses and device nonlinearity, which existing methods struggle to effectively trap and maintain resistivity in the near-surface region.
Innovation Solution
A method is developed to enhance the silicon-on-insulator structure by incorporating a charge trapping layer (CTL) between the high resistivity substrate and buried oxide, using a single crystal semiconductor handle substrate with an epitaxial layer doped with opposite type dopants, followed by deposition of a polycrystalline silicon layer to achieve full depletion and high apparent resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge trapping layer is added between the substrate and buried oxide, then charge trapping efficiency is improved and harmonic distortions are suppressed, but device structure complexity increases
Solution Approach 1:
The substrate structure is segmented into multiple functional layers: the original high resistivity substrate, a newly added epitaxial layer with opposite polarity dopants, and the existing buried oxide layer. This segmentation allows the epitaxial layer to specifically handle charge trapping while the substrate provides mechanical support, resolving the contradiction by distributing functions across layers.
Solution Approach 2:
The invention creates a composite substrate structure combining the high resistivity substrate material with an epitaxial layer of opposite polarity. This composite structure leverages the electrical properties of the substrate and the charge trapping capabilities of the epitaxial layer, achieving effective charge trapping without requiring complex external trapping mechanisms.
2Loss of energy
If ultra-high resistivity substrates are used, then parasitic power losses are reduced, but process and metrology issues increase
Solution Approach 1:
Instead of using ultra-high resistivity substrates that cause manufacturing difficulties, the invention changes the parameter approach by using a moderate resistivity substrate combined with an epitaxial layer of opposite polarity. This parameter change allows the system to achieve low parasitic losses through the epitaxial layer's depletion region rather than relying on extreme substrate resistivity, thus easing manufacturing and metrology requirements.
Solution Approach 2:
The epitaxial layer acts as an intermediary between the substrate and the active device region. It mediates the electrical properties by creating a depletion region that suppresses charge inversion, thereby reducing parasitic losses without requiring the substrate itself to have ultra-high resistivity. This intermediary approach resolves the contradiction by decoupling the substrate's mechanical role from the electrical optimization function.
3Reliability
If the epitaxial layer is fully depleted, then apparent resistivity is enhanced and RF performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The invention uses partial action by doping the epitaxial layer with opposite polarity dopants at a concentration sufficient to create a depletion region that extends through most of the layer thickness. Full depletion is achieved without requiring extremely precise doping control throughout the entire layer, as the critical function is achieved in the depletion region rather than requiring uniform properties throughout. This resolves the contradiction by achieving the necessary effect with moderate precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly improves RF device performance by suppressing second and third harmonic distortions, allowing the use of lower resistivity substrates while maintaining high effective resistivity, thus reducing process and metrology issues associated with ultra-high resistivity wafers.
Implementation Method 1
using a single crystal semiconductor handle substrate with an epitaxial layer doped with opposite type dopants, followed by deposition of a polycrystalline silicon layer to achieve full depletion and high apparent resistivity
Implementation Method 2
incorporating a charge trapping layer (CTL) between the high resistivity substrate and buried oxide
Implementation Method 3
the hydrophilic bond between the donor wafer and handle wafer (i.e., a bonded wafer) is strengthened by heating or annealing the bonded wafer pair
Implementation Method 4
The elevated temperatures cause the formation of covalent bonds between the adjoining surfaces of the donor wafer and the handle wafer, thus solidifying the bond
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~3D
AI summary
A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.