SOI Semiconductor Structure With Charge Traps for RF Linearity
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Solution Overview
Problem
Semiconductor-on-insulator (SOI) technology faces issues with parasitic surface conduction and cross-talk due to parasitic charges accumulating at the oxide/silicon interface, causing harmonic distortion and interference in RF devices.
Innovation Solution
A semiconductor structure is designed with a charge trap layer between the substrate and insulating layer, and a charge trap structure in the active layer surrounding device regions, using trap-rich dielectric materials to prevent parasitic charge accumulation and conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If SOI structure is used to reduce parasitic capacitance, then power-speed performance is improved, but parasitic surface conduction occurs due to charge accumulation at oxide/silicon interface
Solution Approach 1:
A charge trap layer is introduced as an intermediary between the buried oxide layer and the active layer. This charge trap layer captures and holds parasitic charges that would otherwise accumulate at the oxide/silicon interface and cause surface conduction. The charge trap layer acts as a mediator that prevents the harmful interaction between the oxide fixed charges and the silicon substrate, eliminating the parasitic surface conduction pathway while preserving the SOI structure's low parasitic capacitance advantage.
2Ease of manufacture
If conventional SOI structure is used, then manufacturing simplicity is maintained, but signal linearity deteriorates due to harmonic distortion from parasitic charges
Solution Approach 1:
The invention modifies the electrical parameters of the SOI structure by introducing a charge trap layer with specific trap density and depth characteristics. This parameter change allows the structure to maintain its manufacturing simplicity while fundamentally altering the charge distribution profile. The charge trap layer's ability to hold positive charges creates a depletion region that prevents parasitic conduction, thereby improving signal linearity and reducing harmonic distortion without complicating the manufacturing process.
3Manufacturing precision
If charge trap layer is added to prevent parasitic conduction, then signal linearity is improved, but device complexity increases
Solution Approach 1:
The charge trap layer is segmented into specific depth regions within the SOI structure, positioned between the buried oxide and the active layer. This segmentation allows the charge trap functionality to be localized precisely where it is needed to prevent parasitic surface conduction, without unnecessarily complicating the entire device structure. The segmented approach enables selective charge trapping in the critical interface region while maintaining simplicity in other device regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The charge trap layer and structure effectively reduce parasitic surface conduction and cross-talk, improving signal linearity and reducing harmonic distortion in RF devices.
Implementation Method 1
a charge trap layer and a charge trap structure formed on an SOI substrate... trap-rich dielectric materials to prevent parasitic charge accumulation and conduction
Data Source
AI summary
A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer, a plurality of isolation structures in the active layer to define a first device region and a non-device region of the active layer, a first semiconductor device formed on the first device region of the active layer, and a charge trap structure extending through the non-device region of the active layer. In a plane view, the charge trap structure and the non-device region form concentric closed ring surrounding the first device region.